IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 177

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Deinterlacer
Table 6–11. Deinterlacer Signals (Part 3 of 4)
May 2011 Altera Corporation
ma_control_av_writedata
read_master_N_av_address
read_master_N_av_burstcount
read_master_N_av_clock
read_master_N_av_read
read_master_N_av_readdata
read_master_N_av_readdatavalid
read_master_N_av_reset
read_master_N_av_waitrequest
write_master_av_address
write_master_av_burstcount
write_master_av_clock
write_master_av_reset
write_master_av_waitrequest
write_master_av_write
Signal
Direction
In
Out
Out
In
Out
In
In
In
In
Out
Out
In
In
In
Out
ma_control slave port Avalon-MM writedata bus. The
MegaCore function uses these input lines for write
transfers.
read_master_N port Avalon-MM address bus. This bus
specifies a byte address in the Avalon-MM address space.
read_master_N port Avalon-MM burstcount signal. This
signal specifies the number of transfers in each burst. (1),
read_master_N port clock signal. The interface operates
on the rising edge of the clock signal. (1), (2), (3),
read_master_N port Avalon-MM read signal. The
MegaCore function asserts this signal to indicate read
requests from the master to the system interconnect fabric.
read_master_N port Avalon-MM readdata bus. These
input lines carry data for read transfers. (1), (2),
read_master_N port Avalon-MM readdatavalid signal.
The system interconnect fabric asserts this signal when the
requested read data has arrived. (1), (2),
read_master_N port reset signal.
The interface asynchronously resets when this signal is
high. You must deassert this signal synchronously to the
rising edge of the clock signal. (1), (2), (3),
read_master_N port Avalon-MM waitrequest signal.
The system interconnect fabric asserts this signal to cause
the master port to wait. (1), (2),
write_master port Avalon-MM address bus. This bus
specifies a byte address in the Avalon-MM address space.
write_master port Avalon-MM burstcount signal. This
signal specifies the number of transfers in each burst. (1),
write_master port clock signal. The interface operates on
the rising edge of the clock signal. (1), (3),
write_master port reset signal. The interface
asynchronously resets when this signal is high. You must
deassert this signal synchronously to the rising edge of the
clock signal. (1), (3),
write_master port Avalon-MM waitrequest signal. The
system interconnect fabric asserts this signal to cause the
master port to wait. (1),
write_master port Avalon-MM write signal. The
MegaCore function asserts this signal to indicate write
requests from the master to the system interconnect fabric.
(1), (2),
(2),
(1), (2),
(1),
(2),
(1),
(3)
(3)
(3)
(3)
(3)
(3)
(5)
Video and Image Processing Suite User Guide
Description
(4)
(3)
(3)
(3)
(4)
(4)
(3)
(4)
6–13