IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 18

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–10
Table 1–7. Chroma Resampler Performance (Part 2 of 2)
Table 1–8. Clipper Performance
Table 1–9. Clocked Video Input Performance (Part 1 of 2)
Video and Image Processing Suite User Guide
Downsamping from 4:4:4 to 4:2:2 with a sequential data interface at quarter common intermediate format (QCIF - 176x144)
using an anti-aliasing filter.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
A 1080p60-compatible clipper with a clipping window that has fixed offsets from the size of the input frames.
A 100×100 pixel clipper with a clipping window that is a rectangle from the input frames.
A 1080p60-compatible clipper with a run-time interface which uses offsets to set the clipping window.
A 100×100 pixel clipper with a run-time interface which uses a rectangle to set the clipping window.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Converts DVI 1080p60 clocked video to Avalon-ST Video.
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Table
Clipper
Clocked Video Input
(2)
(2)
(2)
(2)
(2)
(2)
1–7:
1–8:
(1)
(1)
(1)
(1)
(1)
(1)
Combinational
Combinational
Combinational
Table 1–8
Table 1–9
LUTs/ALUTs
LUTs/ALUTs
LUTs/ALUTs
596
452
430
355
661
522
577
470
377
296
785
406
shows the performance figures for the Clipper.
shows the performance figures for the Clocked Video Input.
Registers
Registers
Registers
Logic
Logic
Logic
664
453
509
275
817
599
697
446
483
376
872
560
Bits
Bits
51,200
51,200
—
—
—
—
—
—
—
—
—
—
Bits
Memory
Memory
M9K
M9K
—
—
—
—
—
0
0
0
0
0
M9K
—
7
Memory
M20K
M20K
—
—
—
—
—
Chapter 1: About This MegaCore Function Suite
0
0
0
0
0
M20K
—
3
(9×9)
(9x9)
Performance and Resource Utilization
—
—
—
—
—
—
—
—
—
—
DSP Blocks
DSP Blocks
MLAB Bits
May 2011 Altera Corporation
—
—
(18×18)
(18x18)
—
—
—
—
—
—
—
—
—
—
133.24
206.57
(MHz)
210.13
323.31
191.28
313.77
217.72
321.13
194.33
298.78
207.04
334.56
f
(MHz)
(MHz)
MAX
f
f
MAX
MAX