IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 199

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Color Space Converter
Table 7–5. Clocked Video Output Control Register Map (Part 3 of 3)
Color Space Converter
Table 7–6. Color Space Converter Control Register Map (Part 1 of 2)
May 2011 Altera Corporation
22
23
24
25
26
27
28
29
30
Note to
(1) The rows in the table are repeated in ascending order for each video mode. All of the ModeN registers are write only.
0
1
Address
Address
Table
Mode1 Standard
Mode1 SOF Sample
Mode1 SOF Line
Mode1 Vcoclk Divider
Mode1 Ancillary Line
Mode1 F0 Ancillary Line
Mode1 Valid
Mode2 Control
...
Control
Status
7–5:
(1)
Register Name
Register
Table 7–6
function.
The width of each register in the Color Space Converter control register map is 32 bits.
The coefficient and summand registers use integer, signed 2’s complement numbers.
To convert from fractional values, simply move the binary point right by the number
of fractional bits specified in the user interface.
The control data is read once at the start of each frame and is buffered inside the
MegaCore function, so the registers can be safely updated during the processing of a
frame.
describes the control register map for the Color Space Converter MegaCore
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes
the Color Space Converter MegaCore function to stop the next time control information
is read. Refer to
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Slave Interfaces” on page 4–17
The value output on the vid_std signal.
Start of frame sample register. The sample and subsample upon which the SOF
occurs (and the vid_sof signal triggers):
■
■
SOF line register. The line upon which the SOF occurs measured from the rising
edge of the F0 vertical sync.
Number of cycles of vid_clk (vcoclk) before vcoclk_div signal triggers.
The line to start inserting ancillary data packets.
The line in field F0 to start inserting ancillary data packets.
Video mode 1 valid. Set to indicate that this mode is valid and can be used for
video output.
...
...
Bits 0–1 are the subsample value.
Bits 2–15 are the sample value.
“Avalon-MM Slave Interfaces” on page 4–17
for full details.
Description
Description
Video and Image Processing Suite User Guide
for full details.
“Avalon-MM
7–7