IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 201

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Deinterlacer
Table 7–7. Control Synchronizer Control Register Map (Part 2 of 2)
Deinterlacer
Table 7–8. Deinterlacer Control Register Map for Run-Time Control of the Motion-Adaptive Algorithm
May 2011 Altera Corporation
13
14
15
16
17
18
19
20
21
22
23
24
0
1
2
3
Address
Address
Address 4e
Word 4
Address 5
Word 5
Address 6
Word 6
Address 7
Word 7
Address 8
Word 8
Address 9
Word 9
Control
Status
Motion value
override
Blending
coefficient
Register(s)
Register
An run-time control interface can be attached to the Deinterlacer that you can use to
override the default behavior of the motion-adaptive algorithm or to synchronize the
input and output frame rates. However, it is not possible to enable both interfaces
simultaneously.
Table 7–8
algorithm at run time. The control data is read once and registered before outputting a
frame. It can be safely updated during the processing of a frame.
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the
Deinterlacer MegaCore function to stop before control information is read and before
outputting a frame. While stopped, the Deinterlacer may continue to receive and drop
frames at its input if triple-buffering is enabled. Refer to
page 4–17
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Slave Interfaces” on page 4–17
Write-only register. Bit 0 of this register should be set to 1 to override the per-pixel
motion value computed by the deinterlacing algorithm with a user specified value. This
register cannot be read.
Write-only register. The 16-bit value that overrides the motion value computed by the
deinterlacing algorithm. This value can vary between 0 (weaving) to 65535 (bobbing).
The register cannot be read.
Address where word 4 should be written on trigger condition.
The word to write to address 4 on trigger condition.
Address where word 5 should be written on trigger condition.
The word to write to address 5 on trigger condition.
Address where word 6 should be written on trigger condition.
The word to write to address 6 on trigger condition.
Address where word 7 should be written on trigger condition.
The word to write to address 7 on trigger condition.
Address where word 8 should be written on trigger condition.
The word to write to address 8 on trigger condition.
Address where word 9 should be written on trigger condition.
The word to write to address 9 on trigger condition.
describes the control register map that controls the motion-adaptive
for full details.
for full details.
Description
Description
Video and Image Processing Suite User Guide
“Avalon-MM Slave Interfaces” on
“Avalon-MM
7–9