IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 15

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function Suite
MegaCore Verification
MegaCore Verification
Performance and Resource Utilization
Table 1–4. 2D FIR Filter Performance (Part 1 of 2)
May 2011 Altera Corporation
Edge detecting 3×3 asymmetric filter, working on 352×288 8-bit R’G’B’, using 3 bit coefficients.
Smoothing 3×3 symmetric filter, working on 640×480 8-bit R’G’B’, using 9 bit coefficients.
Cyclone IV GX
Cyclone IV GX
Device Family
Stratix V
Stratix V
Test Pattern Generator
Design Example
2D FIR Filter
(2)
(2)
f
1
(1)
(1)
Combinational
The Test Pattern Generator generates a video stream that displays either still color
bars for use as a test pattern or a constant color for use as a uniform background. You
can use this MegaCore function during the design cycle to validate a video system
without the possible throughput issues associated with a real video input.
A provided design example offers a starting point to quickly understand the Altera
video design methodology, enabling you to build full video processing systems on an
FPGA.
For more information about this design example, refer to
Processing Up Conversion Example
Before releasing a version of each MegaCore function, Altera runs comprehensive
regression tests to verify quality and correctness.
Custom variations of the MegaCore functions exercise various parameter options. The
resulting simulation models are thoroughly simulated and the results verified against
bit-accurate master simulation models.
This section shows typical expected performance for the Video and Image Processing
Suite MegaCore functions with the Quartus
Stratix V devices.
Cyclone IV GX devices use combinational look-up tables (LUTs) and logic registers;
Stratix V devices use combinational adaptive look-up tables (ALUTs) and logic
registers.
Table 1–4 on page 1–7
LUTs/ALUTs
984
777
986
771
Registers
Logic
1,341
1,313
987
958
shows the performance figures for the 2D FIR Filter.
16,896
16,896
30,720
30,720
Bits
Design.
Memory
M9K
—
—
4
4
®
II software targeting Cyclone IV GX and
M20K
—
—
2
2
Video and Image Processing Suite User Guide
AN427: Video and Image
(9×9)
—
—
9
6
DSP Blocks
(18×18)
—
—
9
3
302.48
(MHz)
207.9
326.9
f
205
MAX
1–7