IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 123

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Deinterlacer
Deinterlacer
May 2011 Altera Corporation
1
4. The Scaler has been reconfigured to output width 320 frames. The Control
Figure 5–20. Reconfigured Scaler.
You can customize the Control Synchronizer according to the parameters shown in
Table
Table 5–18. Control Synchronizer Parameters
The Deinterlacer MegaCore function converts interlaced video to progressive video
using bob, weave, or motion-adaptive methods. In addition, the Deinterlacer can
provide double or triple-buffering in external RAM. Buffering is required by the
motion-adaptive and weave methods and can be selected if desired when using a bob
method.
You can configure the Deinterlacer to produce one output frame for each input field or
to produce one output frame for each input frame (a pair of two fields). For example,
if the input video stream is NTSC video with 60 interlaced fields per second, the
former configuration outputs 60 frames per second but the latter outputs 30 frames
per second.
Producing one output frame for each input field should give smoother motion but
may also introduce visual artefacts on scrolling text or slow moving objects when
using the bob or motion adaptive algorithm.
Frame Width
Frame Height
Interlaced / Progressive
Bits per Color Sample
Color Pattern
Synchronizer has resumed the video processing pipeline. At no point did the
Scaling ratio change from 1:1, as shown in Figure
5–18.
Parameter
Avalon MM
Test Pattern
Generator
Red Line Indicates Control Data Packet and Video Data Packet Pair Number 14 (Width 320)
Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 5 (Width 320)
Control Data Packet and Video Data Packet Pair Numbers 6 to 13 are Stored in the Frame Buffer
Run-time controlled. Any valid value supported.
Number of bits per color sample selected in the parameter editor.
Up to four color planes in parallel, with any number of color planes in
sequence.
Run-time controlled. Any valid value supported.
Run-time controlled. Any valid value supported.
Nios II CPU
Frame
Buffer
Avalon MM
Master
Synchronizer
Control
Value
Avalon MM
Video and Image Processing Suite User Guide
Figure
5–20.
Scaler
Avalon MM
5–39