IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 184

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–20
Table 6–14. Frame Reader Signals (Part 2 of 2)
Video and Image Processing Suite User Guide
dout_startofpacket
dout_valid
slave_av_address
slave_av_read
slave_av_readdata
slave_av_write
slave_av_writedata
slave_av_irq
master_av_address
master_av_burstcount
master_av_read
master_av_readdata
master_av_readdatavalid
master_av_waitrequest
master_av_reset
master_av_clock
Signal
Direction
Out
Out
In
In
Out
In
In
Out
Out
Out
Out
In
In
In
In
In
dout port Avalon-ST startofpacket signal. This
signal marks the start of an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is
asserted when the MegaCore function outputs data.
slave port Avalon-MM address. Specifies a word offset
into the slave address space.
slave port Avalon-MM read signal. When you assert
this signal, the slave port drives new data onto the read data bus.
slave port Avalon-MM readdata bus. These output
lines are used for read transfers.
slave port Avalon-MM write signal. When you assert
this signal, the gamma_lut port accepts new data from the
writedata bus.
slave port Avalon-MM writedata bus. These input
lines are used for write transfers.
slave port Avalon-MM interrupt signal. When
asserted the interrupt registers of the MegaCore function have
been updated and the master should read them to determine what
has occurred.
master port Avalon-MM address bus. Specifies a byte
address in the Avalon-MM address space.
master port Avalon-MM burstcount signal. Specifies
the number of transfers in each burst.
master port Avalon-MM read signal. Asserted to
indicate read requests from the master to the system interconnect
fabric.
master port Avalon-MM readdata bus. These input
lines carry data for read transfers.
master port Avalon-MM readdatavalid signal. The
system interconnect fabric asserts this signal when the requested
read data has arrived.
master port Avalon-MM waitrequest signal. The
system interconnect fabric asserts this signal to cause the master
port to wait.
master port reset signal. The interface asynchronously
resets when you assert this signal. You must deassert this signal
synchronously to the rising edge of the clock signal.
master port The clock signal. The interface operates on
the rising edge of the clock signal.
Description
May 2011 Altera Corporation
Chapter 6: Signals
Frame Reader