IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 198

MegaCore Suite W/ 17 DSP Video/image Processing Functions

IPS-VIDEO

Manufacturer Part Number
IPS-VIDEO
Description
MegaCore Suite W/ 17 DSP Video/image Processing Functions
Manufacturer
Altera
Type
-r
Datasheets

Specifications of IPS-VIDEO

Software Application
IP CORE, SUITES
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
Suite of IP Functions for Video and Image Processing
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
7–6
Table 7–5. Clocked Video Output Control Register Map (Part 2 of 3)
Video and Image Processing Suite User Guide
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Address
Interrupt
Used Words
Video Mode Match
ModeX Control
Mode1 Sample Count
Mode1 F0 Line Count
Mode1 F1 Line Count
Mode1 Horizontal Front
Porch
Mode1 Horizontal Sync
Length
Mode1 Horizontal
Blanking
Mode1 Vertical Front
Porch
Mode1 Vertical Sync
Length
Mode1 Vertical Blanking
Mode1 F0 Vertical Front
Porch
Mode1 F0 Vertical Sync
Length
Mode1 F0 Vertical
Blanking
Mode1 Active Picture
Line
Mode1 F0 Vertical
Rising
Mode1 Field Rising
Mode1 Field Falling
Register
Bits 2 and 1 are the interrupt status bits:
The used words level of the output FIFO.
One-hot register that indicates the video mode that is selected.
Video Mode 1 Control. Bit 0 of this register is the Interlaced bit:
Bit 1 of this register is the sequential output control bit (only if the Allow output
of color planes in sequence compile-time parameter is enabled).
Video mode 1 sample count. Specifies the active picture width of the field.
Video mode 1 field 0/progressive line count. Specifies the active picture height
of the field.
Video mode 1 field 1 line count (interlaced video only). Specifies the active
picture height of the field.
Video mode 1 horizontal front porch. Specifies the length of the horizontal front
porch in samples.
Video mode 1 horizontal synchronization length. Specifies the length of the
horizontal synchronization length in samples.
Video mode 1 horizontal blanking period. Specifies the length of the horizontal
blanking period in samples.
Video mode 1 vertical front porch. Specifies the length of the vertical front porch
in lines.
Video mode 1 vertical synchronization length. Specifies the length of the vertical
synchronization length in lines.
Video mode 1 vertical blanking period. Specifies the length of the vertical
blanking period in lines.
Video mode 1 field 0 vertical front porch (interlaced video only). Specifies the
length of the vertical front porch in lines.
Video mode 1 field 0 vertical synchronization length (interlaced video only).
Specifies the length of the vertical synchronization length in lines.
Video mode 1 field 0 vertical blanking period (interlaced video only). Specifies
the length of the vertical blanking period in lines.
Video mode 1 active picture line. Specifies the line number given to the first line
of active picture.
Video mode 1 field 0 vertical blanking rising edge. Specifies the line number
given to the start of field 0's vertical blanking.
Video mode 1 field rising edge. Specifies the line number given to the end of
Field 0 and the start of Field 1.
Video mode 1 field falling edge. Specifies the line number given to the end of
Field 0 and the start of Field 1.
When bit 1 is asserted, the status update interrupt has triggered.
When bit 2 is asserted, the locked interrupt has triggered.
The interrupts stay asserted until a write of 1 is performed to these bits.
Set to 1 for interlaced. Set to a 0 for progressive.
Setting bit 1 to 1, enables sequential output from the Clocked Video Output
e.g. for NTSC. Setting bit 1 to a 0, enables parallel output from the Clocked
Video Output e.g. for 1080p.
Description
Chapter 7: Control Register Maps
May 2011 Altera Corporation
Clocked Video Output

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