IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 181

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Frame Buffer
Table 6–12. Deinterlacer II Signals (Part 4 of 4)
Frame Buffer
Table 6–13. Frame Buffer Signals (Part 1 of 3)
May 2011 Altera Corporation
write_master_waitrequest
motion_write_master_address
motion_write_master_write
motion_write_master_burstcount
motion_write_master_writedata
motion_write_master_waitrequest
Note to
(1) Two read master interfaces are used: edi_read_master and ma_read_master.
(2) When you select Motion Adaptive High Quality or Motion Adaptive, one additional read master (motion_read_master) and one additional
(3) Additional av_mm_clock and av_mm_reset signals are available when you turn on Use separate clocks for the Avalon-MM master
(4) The signals associated with the control slave port are not present unless you enable Run-time control.
clock
reset
din_data
din_endofpacket
din_ready
din_startofpacket
write master (motion_write_master) ports are used to read and update motion values.
interface(s).
Table
6–12:
Signal
Signal
Table 6–13
function.
shows the input and output signals for the Frame Buffer MegaCore
Direction
In
In
In
In
Out
In
Direction
In
Out
Out
Out
Out
In
The main system clock. The MegaCore function operates on the
rising edge of the clock signal.
The MegaCore function asynchronously resets when you assert
reset. You must deassert reset synchronously to the rising
edge of the clock signal.
din port Avalon-ST data bus. This bus enables the transfer of
pixel data into the MegaCore function.
din port Avalon-ST endofpacket signal. This signal marks the
end of an Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates when the
MegaCore function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal marks the
start of an Avalon-ST packet.
write_master port Avalon-MM waitrequest signal. The
system interconnect fabric asserts this signal to cause the
master port to wait.
motion_write_master port Avalon-MM address bus.
This bus specifies a byte address in the Avalon-MM
address space.
motion_write_master port Avalon-MM write signal.
The MegaCore function asserts this signal to indicate write
requests from the master to the system interconnect
fabric.
motion_write_master port Avalon-MM burstcount
signal. This signal specifies the number of transfers in each
burst.
motion_write_master port Avalon-MM writedata bus.
These output lines carry data for write transfers.
motion_write_master port Avalon-MM waitrequest
signal.The system interconnect fabric asserts this signal to
cause the master port to wait.
(2)
(2)
(2)
Description
Video and Image Processing Suite User Guide
Description
(2)
(2)
6–17