IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 202

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

7–10
Table 7–9. Deinterlacer Control Register Map for Synchronizing the Input and Output Frame Rates
Deinterlacer II
Table 7–10. Deinterlacer II Control Register Map for Run-Time Control of the Motion-Adaptive Algorithm
Frame Buffer
Video and Image Processing Suite User Guide
0
1
2
3
Note to
(1) The behavior of the rate conversion algorithm is not directly affected by a particular choice of input and output rates but only by their ratio.
0
1
2
3
4
Address
Address
23.976 -> 29.970 is equivalent to 24 -> 30.
Table
Control
Status
Input frame
rate
Output frame
rate
Control
Status
Reserved
Cadence detect on
Cadence detected
7–9:
Register
Register
Table 7–8
frame rates. The control data is read and registered when receiving the image data
header that signals new frame. It can be safely updated during the processing of a
frame.
Table 7–10
Deinterlacer II reads the control data once at the start of each frame and buffers the
data inside the MegaCore function. The registers may safely update during the
processing of a frame.
A run-time control can be attached either to the writer component or to the reader
component of the Frame Buffer MegaCore function but not to both. The width of each
register is 16 bits.
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the
Deinterlacer MegaCore function to stop before control information is read and before
receiving and buffering the next frame. While stopped, the Deinterlacer may freeze the
output and repeat a static frame if triple-buffering is enabled. Refer to
Interfaces” on page 4–17
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Slave Interfaces” on page 4–17
Write-only register. An 8-bit integer value for the input frame rate This register cannot be
read.
Write-only register. An 8-bit integer value for the output frame rate. The register cannot be
read.
describes the control register map that synchronizes the input and output
describes the Deinterlacer II MegaCore function control register map. The
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes
the Deinterlacer II to stop after generating the current output frame.
Bit 0 of this register is the Status bit, all other bits are unused. When this bit is set
to 0, the Deinterlacer II either gets disabled through the Go bit or waits to receive
video data.
This register is reserved for future use.
Setting bit 0 of this register to 1 enables cadence detection. Setting bit 0 of this
register to 0 disables cadence detection. Cadence detection is disabled on reset.
Reading a 1 from bit 0, indicates that the Deinterlacer II has detected a cadence and
is performing reverse telecine. Reading a 0 indicates otherwise.
(1)
(1)
for full details.
for full details.
Description
Description
Chapter 7: Control Register Maps
May 2011 Altera Corporation
“Avalon-MM Slave
“Avalon-MM
Deinterlacer II