IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 174

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–10
Table 6–9. Color Space Converter Signals (Part 2 of 2)
Control Synchronizer
Table 6–10. Control Synchronizer Signals (Part 1 of 2)
Video and Image Processing Suite User Guide
din_ready
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
clock
reset
din_data
din_endofpacket
din_ready
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
Signal
Signal
Table 6–10
MegaCore function.
Direction
Out
In
In
Out
Out
In
Out
Out
In
In
In
In
Out
In
In
Out
Out
in
Direction
shows the input and output signals for the Control Synchronizer
din port Avalon-ST ready signal. This signal indicates when the MegaCore
function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal marks the start of an
Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the cycles when the port
should input data.
dout port Avalon-ST data bus. This bus enables the transfer of pixel data out of
the MegaCore function.
dout port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
dout port Avalon-ST ready signal. The downstream device asserts this signal
when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks the start of an
Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when the MegaCore
function outputs data.
The main system clock. The MegaCore function operates on the rising edge of
the clock signal.
The MegaCore function asynchronously resets when you assert reset. You
must deassert reset synchronously to the rising edge of the clock signal.
din port Avalon-ST data bus. This bus enables the transfer of pixel
data into the MegaCore function.
din port Avalon-ST endofpacket signal. This signal marks the end
of an Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates when the
MegaCore function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal marks the
start of an Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the cycles
when the port should input data.
dout port Avalon-ST data bus. This bus enables the transfer of pixel
data out of the MegaCore function.
dout port Avalon-ST endofpacket signal. This signal marks the
end of an Avalon-ST packet.
dout port Avalon-ST ready signal. The downstream device asserts
this signal when it is able to receive data.
Description
Description
May 2011 Altera Corporation
Control Synchronizer
Chapter 6: Signals