EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 123

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 6–13. Phase Relationship Between PLL Clocks in Normal Mode
Note to
(1)
Altera Corporation-Preliminary
March 2007
The external clock output can lead or lag the PLL internal clock signals.
Figure
6–13:
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin.
The external clock output pin has a phase delay relative to the clock input
pin if connected in this mode. The Quartus II software timing analyzer
reports any phase difference between the two. In normal mode, the PLL
fully compensates the delay introduced by the GCLK network.
Figure 6–13
relationship in this mode.
Zero Delay Buffer (ZDB) Mode
In the zero delay buffer mode, the external clock output pin is phase-
aligned with the clock input pin for zero delay through the device. When
using this mode, you must use the same I/O standard on the input clock
and output clocks in order to guarantee clock alignment at the input and
output pins.
shows a waveform example of the PLL clocks' phase
Cyclone III Device Handbook, Volume 1
Note (1)
Clock Feedback Modes
6–23