EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 305

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 10–23. FPP Configuration Timing Waveform
Notes to
(1)
(2)
(3)
(4)
(5)
Altera Corporation-Preliminary
March 2007
t
t
t
t
t
t
t
t
t
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
DSU
DH
Table 10–13. FPP Timing Parameters for Cyclone III Devices (Part 1 of 2)
Symbol
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Cyclone III device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the dual-
purpose pin settings.
CONF_DONE (3)
Figure
nSTATUS (2)
INIT_DONE
nCONFIG
nCONFIG
nCONFIG
nSTATUS
nCONFIG
nCONFIG
nSTATUS
Data setup time before rising edge on
Data hold time after rising edge on
DATA[7..0]
nCONFIG
DCLK
User I/O
10–23:
low to
low to
low pulse width
low pulse width
high to
high to first rising edge on
high to first rising edge of
t
t
CF2CD
CFG
t
Parameter
Table 10–13
configuration.
CF2ST1
CONF_DONE
nSTATUS
t
CF2ST0
nSTATUS
t
CF2CK
t
ST2CK
t
Byte 0
STATUS
t
High-Z
CH
t
CLK
t
DSU
t
Byte 1
low
CL
high
t
DH
defines the timing parameters for Cyclone III devices for FPP
low
Byte 2
DCLK
DCLK
DCLK
Byte 3
DCLK
Note (1)
230
Min
500
70
2
5
0
Byte n
(2)
Cyclone III Device Handbook, Volume 1
Fast Passive Parallel Configuration
t
CD2UM
Note (1)
230
230
Max
500
500
(2)
(2)
(5)
User Mode
User Mode
(4)
Units
ns
ns
ns
ns
ns
µs
µs
µs
µs
10–69