EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 67

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 4–10. Cyclone III Simple Dual-Port Timing Waveforms
Altera Corporation-Preliminary
March 2007
q (asynch)
wraddress
rdaddress
wrclock
rdclock
wren
data
rden
doutn-1
din-1
an-1
bn
an
din
In simple dual-port mode, M9K memory blocks support separate
write-enable and read-enable signals. You can save power by keeping the
read-enable signal low (inactive) when not reading. Read-during-write
operations to the same address can either output “Don’t Care” data at
that location or output “Old Data”. To choose the desired behavior, set the
Read-During-Write option to either “Don’t Care” or “Old Data” in the
RAM MegaWizard in the Quartus II software. See
Operations” on page 4–28
Figure 4–10
simple dual-port mode with unregistered outputs. Registering the RAM's
outputs would simply delay the q output by one clock cycle.
True Dual-Port Mode
True dual-port mode supports any combination of two-port operations:
two reads, two writes, or one read and one write, at two different clock
frequencies.
configuration.
doutn
b0
a0
shows timing waveforms for read and write operations in
Figure 4–11
a1
shows Cyclone III true dual-port memory
dout0
for more details about this behavior.
a2
b1
Cyclone III Device Handbook, Volume 1
a3
din4
b2
a4
“Read-During-Write
din5
Memory Modes
a5
b3
a6
din6
4–13