EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 287

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 10–15. Multi-Device PS Configuration Using an External Host
Notes to
(1)
(2)
(3)
(4)
(5)
Altera Corporation-Preliminary
March 2007
(MAX II Device or
Microprocessor)
External Host
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. V
Connect the pull-up resistor to the V
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
refer to
All I/O inputs must maintain a maximum AC voltage of 4.1 V. The DATA[0] and DCLK has to fit the maximum
overshoot equation outlined in
ADDR
Figure
Table 10–10 on page
Memory
CC
should be high enough to meet the V
10–15:
DATA[0]
10kΩ
V
CCIO (1)
1
In multi-device PS configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle. Therefore, the transfer of data destinations is transparent
to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[0], and CONF_DONE) are connected to every device in the
chain. Configuration signals can require buffering to ensure signal
10–46. Connect the MSEL pins directly to V
10kΩ
V
“Configuration and JTAG Pin I/O Requirements” on page
CCIO (1)
GND
CCIO
All I/O inputs must maintain a maximum AC voltage of 4.1 V.
In multi-device PS configuration, the DATA[0] and DCLK has to
fit the maximum overshoot equation outlined in
and JTAG Pin I/O Requirements” on page
connect the repeater buffers between the Cyclone III master and
slave device(s) for DATA[0] and DCLK.
Buffers (5)
supply voltage of I/O bank that the nCEO pin resides in.
Cyclone III Device 1
CONF_DONE
nCE
DATA[0] (5)
nCONFIG
DCLK (5)
nSTATUS
IH
specification of the I/O on the device and the external host.
MSEL[3..0]
nCEO
(4)
Cyclone III Device Handbook, Volume 1
CCIO
V
CCIO(2)
or ground.
10 kΩ
Passive Serial Configuration
Cyclone III Device 2
CONF_DONE
nSTATUS
nCE
DATA[0] (5)
nCONFIG
DCLK (5)
10–13. You must
MSEL[3..0]
10–13.
nCEO
“Configuration
N.C. (3)
10–51
(4)