EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 40

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Logic Elements and Logic Array Blocks in Cyclone III Devices
Figure 2–8. LAB-Wide Control Signals
2–10
Cyclone III Device Handbook, Volume 1
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Synchronous clear and load signals are useful for implementing counters
and other functions. The synchronous clear and synchronous load signals
are LAB-wide signals that affect all registers in the LAB.
Each LAB can use two clocks and two clock enable signals. Each LAB's
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal also uses labclkena1. If the
LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. Deasserting the clock enable signal turns off the
LAB-wide clock.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrack™ interconnect's inherent low
skew allows clock and control signal distribution in addition to data
distribution.
LAB-wide signals control the logic for the register’s clear signal. The LE
directly supports an asynchronous clear function. Each LAB supports up
to two asynchronous clear signals (labclr1 and labclr2).
A LAB-wide asynchronous load signal to control the logic for the
register's preset signal is not available. The register preset is achieved by
using a NOT gate push-back technique. Cyclone III devices can only
support either a preset or asynchronous clear signal.
6
labclk1
labclkena1
Figure 2–8
labclk2
shows the LAB control signal generation circuit.
labclkena2
syncload
Altera Corporation-Preliminary
labclr1
labclr2
March 2007
synclr