EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 459

no-image

EP3C16F256I7

Manufacturer Part Number
EP3C16F256I7
Description
Cyclone III
Manufacturer
Altera
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F256I7
Manufacturer:
ALTERA
0
Part Number:
EP3C16F256I7
Manufacturer:
ALTERA
Quantity:
20 000
Part Number:
EP3C16F256I7N
Manufacturer:
IR
Quantity:
14 520
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA31
Quantity:
214
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA
Quantity:
90
Part Number:
EP3C16F256I7N
Manufacturer:
XILINX
0
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA
0
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP3C16F256I7N
0
Cyclone III Device Datasheet: DC & Switching Characteristics
Typical Design
Performance
Altera Corporation-Preliminary
March 2007
Notes to
(1)
(2)
(3)
Input Delay
from Pin to
Internal
Cells
Input Delay
from Pin to
Input
Register
Delay from
Output
Register to
Output Pin
Parameter
Table 1–47. Cyclone III IOE Programmable Delay on Row Pins (1),
The incremental values for the settings are generally linear. For exact values of each setting, please use the latest version of
Quartus II software.
The minimum and maximum offset timing numbers are in reference to setting "0" as available in the Quartus II software.
The fast corner timing parameter is for commercial devices.
Table
Pad -> I/O
dataout to
core
Pad -> I/O
input
register
I/O output
register ->
Pad
Affected
1–47:
Paths
f
Settings
Number
User I/O Pin Timing Parameters
Table 1–48
I/O buffer t
by global clock and a PLL. Device EP3C5 is not available for the current
version of Quartus II.
The 12 μA programmable current strength for 1.2 V and 1.2-V HSTL Class
I I/O standard is not supported at row I/Os. The 1.2-V HSTL Class II
standard is only supported at column I/Os. PCI and PCI-X do not
support programmable current strength.
For more information about programmable current strength, please refer
to the
Dedicated LVDS, mini-LVDS, PPDS, and RSDS I/O standards are
supported at row I/Os. External resistor networks are required if the
differential standards are used as output pins at column banks. LVDS I/O
standard is supported at both input and output pins. PPDS, RDSD, and
mini-LVDS standards are only supported at output pins.
of
7
8
2
Cyclone III Device I/O Features
Fast Corner
Offset
Min
0
0
0
to
SU
Table 1–89
,
t
H
Offset
2352
2802
Max
324
and
(3)
t
CO
show user I/O pin timing for Cyclone III devices.
-6 Speed Grade
Offset
are reported for the cases when clock is driven
Min
0
0
0
Offset
3776
4482
Max
572
(2)
chapter of the Cyclone III Handbook.
-7 Speed Grade
Offset
Min
0
0
0
Offset
4033
4671
Max
626
Cyclone III Handbook
-8 Speed Grade
Offset
Min
0
0
0
Offset
4290
4859
Max
1–49
682
Unit
ps
ps
ps

Related parts for EP3C16F256I7