EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 327

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
DCLK
DATA[0]
Table 10–21. Dedicated Configuration Pins on the Cyclone III Device (Part 4 of 7)
Pin Name
N/A
N/A in AS
mode. I/O in
non-AS
mode
User Mode
PS, FPP, AS,
AP
PS, FPP, AS,
AP
Configuration
Scheme
Input (PS,
FPP). Output
(AS, AP)
Input (PS,
FPP, AS).
Bidirectional
open-drain
(AP)
Pin Type
In PS and FPP configuration,
clock input used to clock data from an external
source into the target Cyclone III device. Data
is latched into the device on the rising edge of
DCLK
In AS and AP mode,
the Cyclone III device that provides timing for
the configuration interface. Optionally, in AS
and AP mode,
core in user-mode. In AS mode,
internal pull-up resistor (typically 25 kΩ) that is
always active.
After configuration, this pin is tri-stated. In
schemes that use a configuration device,
DCLK
done. In schemes that use a control host,
DCLK
whichever is more convenient. Toggling this
pin after configuration does not affect the
configured device.
Data input. In serial configuration modes, bit-
wide configuration data is presented to the
target Cyclone III device on the
In AS mode,
resistor that is always active. After AS
configuration,
pin with optional user control.
After PS or FPP configuration,
available as a user I/O pin and the state of this
pin depends on the Dual-Purpose Pin
settings.
After AP configuration,
dedicated bidirectional pin with optional user
control.
Cyclone III Device Handbook, Volume 1
.
will be driven low after configuration is
should be driven either high or low,
DATA[0]
DATA[0]
DCLK
Description
Device Configuration Pins
DCLK
can be controlled by the
DATA[0]
has an internal pull-up
is a dedicated input
is an output from
DCLK
DATA[0]
DATA[0]
DCLK
is a
is the
has an
10–91
pin.
is