EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 5

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Chapter Revision Dates .......................................................................... iii
About this Handbook ............................................................................. xiii
Section I. Device Core
Chapter 1. Cyclone III Device Family Overview
Chapter 2. Logic Elements and Logic Array Blocks in Cyclone III Devices
Altera Corporation
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Cyclone III: Lowest System-Cost FPGAs ........................................................................................... 1–1
Features ................................................................................................................................................... 1–1
Cyclone III Device Architecture .......................................................................................................... 1–5
Reference and Ordering Information ............................................................................................... 1–13
Document Revision History ............................................................................................................... 1–14
Introduction ............................................................................................................................................ 2–1
Overview ................................................................................................................................................. 2–1
Logic Elements ....................................................................................................................................... 2–1
Reduced Cost .................................................................................................................................... 1–1
Lowest-Power 65-nm FPGA ........................................................................................................... 1–1
Increased System Integration ......................................................................................................... 1–1
LEs and LABs .................................................................................................................................... 1–6
MultiTrack Interconnect .................................................................................................................. 1–7
Memory Blocks ................................................................................................................................. 1–7
Embedded Multipliers and Digital Signal Processing Support ................................................ 1–7
I/O Features ...................................................................................................................................... 1–9
Clock Networks and PLLs .............................................................................................................. 1–9
High-Speed Differential Interfaces .............................................................................................. 1–10
Auto-Calibrating External Memory Interfaces .......................................................................... 1–10
Quartus II Software Support ........................................................................................................ 1–11
Nios II – The World’s Most Versatile Embedded Processor .................................................... 1–11
Configuration .................................................................................................................................. 1–11
Remote System Upgrades ............................................................................................................. 1–12
Hot Socketing and Power-On-Reset ............................................................................................ 1–12
SEU Mitigation ................................................................................................................................ 1–13
JTAG Boundary Scan Testing ....................................................................................................... 1–13
LE Features ........................................................................................................................................ 2–2
Contents
v