EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 140

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
6–40
Cyclone III Device Handbook, Volume 1
1
Post-Scale Counters (c0 to c4)
The multiply or divide values and duty cycle of post-scale counters can
be configured in real time. Each counter has an 8-bit high time setting and
an 8-bit low time setting. The duty cycle is the ratio of output high or low
time to the total cycle time, which is the sum of the two. Additionally,
these counters have two control bits, rbypass, for bypassing the counter,
and rselodd, to select the output clock duty cycle.
When the rbypass bit is set to 1, it bypasses the counter, resulting in a
divide by 1. When this bit is set to 0, the PLL computes the effective
division of the VCO output frequency based on the high and low time
counters. For example, if the post-scale divide factor is 10, the high and
low count values could be set to 5 and 5 respectively, to achieve a 50-50%
duty cycle. The PLL implements this duty cycle by transitioning the
output clock from high to low on the rising edge of the VCO output clock.
However, a 4 and a 6 setting for the high and low count values,
respectively, would produce an output clock with 40-60% duty cycle.
The rselodd bit indicates an odd divide factor for the VCO output
frequency along with a 50% duty cycle. For example, if the post-scale
divide factor is 3, the high and low time count values is 2 and 1
respectively to achieve this division. This implies a 67%-33% duty cycle.
If you need a 50%-50% duty cycle, you must set the rselodd control bit
to 1 to achieve this duty cycle despite an odd division factor. The PLL
implements this duty cycle by transitioning the output clock from high to
low on a falling edge of the VCO output clock. When you set
rselodd = 1, you subtract 0.5 cycles from the high time and you add 0.5
cycles to the low time. For example:
■
■
■
High time count = 2 cycles
Low time count = 1 cycle
rselodd = 1 effectively equals:
●
●
●
When reconfiguring the counter clock frequency, the
corresponding counter phase shift settings cannot be
reconfigured using the same interface. You can reconfigure
phase shifts in real time using the dynamic phase shift
reconfiguration interface. If you reconfigure the counter
frequency, but wish to keep the same non-zero phase shift
setting (for example, 90 degrees) on the clock output, then you
will need to reconfigure the phase shift after reconfiguring the
counter clock frequency.
High time count = 1.5 cycles
Low time count = 1.5 cycles
Duty cycle = (1.5/3) % high time count and (1.5/3) % low time
count
Altera Corporation- Preliminary
March 2007