EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 269

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
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For information on the operation of the StrataFlash Embedded Memory
(P30) flash memories from Intel, search for the key word “P30” on the
Intel web site at www.intel.com to obtain the P30 family datasheet.
For information on the operation of the S29WSxxxN MirrorBit flash
memories from Spansion, search for the key word “S29WS-N” on the
Spansion web site at www.spansion.com to obtain the S29WS-N family
datasheet. Refer to the 128N or 256N datasheet.
Single Device AP Configuration
The three groups of interface pins supported in the Intel P30 and
Spansion S29WS-N flash memories are the control pins, the address pins,
and the data pins. In the AP configuration scheme, both of the supported
parallel flash memories accept DCLK, active-low reset (RST# or RESET#),
active-low chip enable (CE#), active-low output enable (OE#), active-low
address valid (ADV# or AVD#), and active-low write enable (WE#) as
control signals from the Cyclone III device. The supported parallel flash
memories output a control signal (WAIT or RDY) to the Cyclone III device
to indicate when synchronous data is ready on the data bus. The
Cyclone III device has a 24-bit address bus which connects to the address
bus (A[24:1] or A[23..0]) of the flash memory. A 16-bit bidirectional
data bus (DATA[15..0]) provides data transfer between the Cyclone III
device and the flash memory.
The control signals from the Cyclone III device to the flash memory
include DCLK, nRESET, FLASH_nCE, nOE, nAVD, and nWE. The interface
for the Intel P30 flash memory and the Spansion S29WS-N flash memory
connects to Cyclone III device pins, as shown in
Figure 10–9
respectively.
Active Parallel Configuration (Supported Flash Memories)
Cyclone III Device Handbook, Volume 1
Figure 10–8
and
10–33