EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 194

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

High-Speed Differential Interfaces in Cyclone III Devices
8–4
Cyclone III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
LVDS
RSDS
mini-LVDS
PPDS
LVPECL
Differential SSTL-2
Differential SSTL-18
Differential HSTL-18
Differential HSTL-15
Differential HSTL-12
Table 8–1. Performance Targets for Various Differential I/O Standards
Differential I/O
"Adj." denotes the dedicated differential output drivers with p and n pins located adjacent to each other. "Sep."
denotes the dedicated differential output drivers with p and n pins not located adjacent to each other. "Res." denotes
the differential output drivers that require an external resistor network. Refer to the pin tables on the Altera web site
(www.altera.com) for details on the location of these pins.
The LVPECL I/O standard is only supported on dedicated clock input pins.
The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input
pins and PLL output clock pins.
The performance target is pending device characterization.
Standards
Table
(2)
8–1:
(3)
(3)
(3)
(3)
(3)
Location
I/O Bank
1,2,5,6
1,2,5,6
3,4,7,8
1,2,5,6
1,2,5,6
3,4,7,8
3,4,7,8
1,2,5,6
1,2,5,6
3,4,7,8
1,2,5,6
1,2,5,6
3,4,7,8
1,2,5,6
3,4,7,8
All
All
All
All
All
Package
Pintable
Note
Sep.
Res.
Sep.
Res.
Res.
Sep.
Res.
Sep.
Res.
Adj.
Adj.
Adj.
Adj.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(1)
External Resistor
Three resistors
Three resistors
Three resistors
Three resistors
Single resistor
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Transmitter
Network at
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Altera Corporation-Preliminary
Not supported
Transmitter
(TX)
840
640
640
360
400
440
200
200
267
200
200
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
Fmax (Mbps)
March 2007
supported
supported
supported
Receiver
(RX)
875
875
875
875
200
200
267
200
200
Not
Not
Not
(4)