HC230F1020 Altera, HC230F1020 Datasheet - Page 144

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
## Example Global Assignments Script for a HardCopy II Design
## This Script Applies Settings for a EP2S90 Stratix II
## prototype FPGA target and a HC230 HardCopy II target
## Source Design File Settings
## ===========================
set_global_assignment -name VERILOG_FILE demo_design.v
set_global_assignment -name VERILOG_FILE example_ram.v
## Stratix II Prototype FPGA Target Settings
## =========================================
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name DEVICE EP2S90F1020C4
set_global_assignment -name TOP_LEVEL_ENTITY demo_design
## HardCopy II Companion Revision and Target Settings
## ==================================================
set_global_assignment -name COMPANION_REVISION_NAME \
set_global_assignment -name DEVICE_TECHNOLOGY_MIGRATION_LIST HC230F1020
## Design Assistant Assignments and Settings Required for HardCopy II
##==============================================================
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name REPORT_IO_PATHS_SEPARATELY ON
## The following assignments are Classic Timing Analyzer only
## and are not used by TimeQuest.
##===========================================================
set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK ON
set_global_assignment -name DO_COMBINED_ANALYSIS ON
set_global_assignment -name IGNORE_CLOCK_SETTINGS OFF
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
## End of Script
6–16
Example Tcl Script for Making Global Assignments
The example Tcl script below illustrates the application of global
constraints for a HardCopy II project.
demo_design_hardcopyii
Altera Corporation
September 2008