HC230F1020 Altera, HC230F1020 Datasheet - Page 81

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

PLL Timing
Specifications
Altera Corporation
September 2008
f
f
f
f
t
t
t
f
t
f
t
f
IN
INPFD
INDUTY
EINDUTY
INJITTER
OUTJITTER
FCOMP
OUT
OUTDUTY
SCANCLK
CONFIGEPLL
OUT_EXT
Table 4–42. HardCopy II Enhanced PLL Specifications (Part 1 of 2)
Name
Input clock frequency for HC210,
HC220, HC230 and HC240 devices
Input clock frequency for the
HC210W device
Input frequency to the PFD
Input clock duty cycle
External feedback input clock duty
cycle
Input or external feedback clock
input jitter tolerance in terms of
period jitter. Bandwidth ≤ 0.85 MHz
Input or external feedback clock
input jitter tolerance in terms of
period jitter. Bandwidth > 0.85 MHz
Dedicated clock output period jitter
for HC210, HC220, HC230 and
HC240 devices
Dedicated clock output period jitter
for HC210W device
External feedback compensation
time
Output frequency for internal global
or regional clock
Duty cycle for external clock output
(when set to 50%).
Scanclk frequency
Time required to reconfigure scan
chains for enhanced PLLs
PLL external clock output
frequency
Tables 4–42
operating in both the commercial junction temperature range (0° to 85° C)
and the industrial junction temperature range (–40° to 100° C), except for
the clock switchover feature. Like the Stratix II devices, the clock
switchover feature is only supported from the 0° to 100° C junction
temperature range.
Description
and
4–43
describe the HardCopy II PLL specifications when
1.5
1.5
Min
40
40
45
—
—
—
—
—
—
—
2
2
2
(2)
(2)
174/f
Typ
0.5
—
—
—
—
—
—
—
50
—
SCANCLK
—
—
—
1
25 mUI for < 100 MHz
30 mUI for < 100 MHz
250 ps for ≥ 100 MHz
300 ps for ≥ 100 MHz
PLL Timing Specifications
320
outclk
outclk
outclk
outclk
Max
500
420
550
100
60
60
10
55
(1)
—
—
—
(1)
ps or
ps or
MHz
MHz
MHz
MHz
MHz
MHz
Unit
(pp)
(pp)
mUI
mUI
ns
ns
ns
ns
%
%
%
4–39