HC230F1020 Altera, HC230F1020 Datasheet - Page 171

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Figure 7–1. Stratix II First Timing Closure Flow
Note to
(1)
Altera Corporation
September 2008
Timing constraints are required in Stratix II revision and HardCopy II revision. The TimeQuest timing analyzer
supports industry-standard SDC files (.sdc) and Classic Timing Analyzer supports Quartus Setting File (.qsf).
Figure
7–1:
As you can see from
the Quartus II design flow. During the Stratix II FPGA prototype
compilation, these constraints are used as the timing target for
timing-driven compilation. When the compilation is complete, the
TimeQuest timing analyzer or Classic Timing Analyzer reports timing
results for your design. Any failed timing reports mean that you must
either modify your timing constraints, change your compile settings and
recompile, or both. In addition, the timing constraint checkers in both
TimeQuest and Classic Timing Analyzer report the unconstrained timing
paths. See
details. For timing verification in third-party tools, the Quartus II
Stratix II Revision
Timing Constraints
HardCopy II Revision
Timing Constraints
Industry Standard
SDC Timing
Constraints
“Using the TimeQuest Timing Analyzer” on page 7–8
Note (1)
Figure
Constraint Coverage Checks
Constraint Coverage Checks
HardCopy II Design Setup
7–1, timing constraints are used very early in
HardCopy Design Center
Stratix II Design Setup
Static Timing Analysis
Static Timing Analysis
Revision Comparison
FPGA Prototyping
Compilation
Compilation
HardCopy II Timing Closure Methodology
Handoff
for
7–7