HC230F1020 Altera, HC230F1020 Datasheet - Page 67

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Maximum
Output Clock
Rates
Altera Corporation
September 2008
Notes to
(1)
(2)
(3)
HyperTransport
3.3-V LVTTL
3.3-V LVCMOS
Table 4–34. HardCopy II Maximum Input Clock Rates of HC210W Devices
Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices
Note (1)
I/O Standard
The PCI clamping diode is only supported on the top and bottom I/O pins.
For HC210W, differential HSTL/SSTL input is supported on the top clock pins, the DQS pins on the top I/O banks and
top/bottom PLL_FB input pins.
These numbers are preliminary and pending further silicon characterization.
Table
I/O Standard
(Part 1 of 5)
4–34:
24 mA
24 mA
Strength
12 mA
16 mA
20 mA
12 mA
16 mA
20 mA
Drive
4 mA
8 mA
4 mA
8 mA
(3)
(3)
Tables 4–35
HardCopy II I/O's for all available drive strengths.
Interface
Memory
IOEs
1040
225
355
475
594
700
794
250
480
710
925
985
Interface
Memory
IOEs
—
and
Speed
High
IOEs
225
355
475
250
480
—
—
—
—
—
—
—
Speed
High
IOEs
320
4–36
Column
General Purpose
Bottom
show the maximum output toggle rates of
225
355
475
250
480
—
—
—
—
—
—
—
Purpose
General
IOEs
—
IOEs
Right
Row
225
355
475
250
480
—
—
—
—
—
—
—
8..11]
[0..3,
CLK
320
CLK [0,
10]
2, 8,
225
355
475
250
480
—
—
—
—
—
—
—
(2)
12..15]
[4..7,
Maximum Output Clock Rates
CLK
Note (3)
—
12..15]
[4..7,
1040
CLK
225
355
475
594
700
794
250
480
710
925
985
FPLL_C
320
(Part 2 of 2)
LK
PLL_OUT
1040
594
700
794
710
925
985
225
355
475
250
480
PLL_FB
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
4–25
MHz
Unit