HC230F1020 Altera, HC230F1020 Datasheet - Page 28

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
Figure 2–6. I/O Type Support in HC240 Devices
Notes to
(1)
(2)
2–20
Preliminary
In addition to supporting external memory interfaces, memory interface IOEs have the same features as general
purpose IOEs. In addition to supporting high-speed I/O interfaces, high-speed IOEs have the same features as
general purpose IOEs, except for the PCI clamping diode and LVPECL clock input support.
This is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is a graphical
representation only.
High-Speed IOEs
High-Speed IOEs
Figures 2–4
Bank 2
Bank 1
through 2–6:
PLL 1
PLL 2
PLL 7
PLL 8
Memory Interface IOEs
Memory Interface IOEs
1
General Purpose IOE
The general purpose IOEs in HC210 and HC220 devices are located on the
right side and at the bottom of the device. The general purpose IOEs in
HC230 devices are located on the right side of the device. (Directions are
based on a top view of the silicon die.) HC240 devices do not have general
purpose IOEs. The general purpose IOE functionality is supported in the
memory interface IOEs for these devices. The high-speed IOEs also
I/O Banks 1 & 2 Support 3.3-,
2.5- & 1.8-V LVTTL/LVCMOS,
1.5-V LVCMOS, LVDS &
HyperTransport Technology
Bank 3
Bank 8
CLK, PLL_FB input pins SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST,
When planning I/O placement for designs targeting
HardCopy II devices, care should be taken to ensure the same
I/O standards are supported in the same HardCopy II I/O
banks as in the Stratix II I/O banks.
differential SSTL and differential HSTL I/O standards.
LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards.
LVDS & HyperTransport technology. CLK & PLL_FB
differential SSTL and differential HSTL I/O standards.
I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/
I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/
LVDS & HyperTransport technology. CLK & PLL_FB
LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V
pins support differential SSTL, differential HSTL,
pins support differential SSTL, differential HSTL,
HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards.
pins support LVPECL. DQS input pins support
pins support LVPECL. DQS input pins support
CLK, PLL_FB input pins & PLL_OUT output
Bank 12 Bank 10
Bank 11 Bank 9
PLL 12
PLL 11
& PLL_OUT output
Notes
PLL 5
PLL 6
(1),
I/O Banks 5 & 6 Support 3.3-,
2.5- & 1.8-V LVTTL/LVCMOS,
(2)
HyperTransport Technology
1.5-V LVCMOS, LVDS &
Memory Interface IOEs
Memory Interface IOEs
Bank 4
Bank 7
PLL 10
PLL 4
PLL 3
PLL 9
Altera Corporation
September 2008
Bank 5
High-Speed IOEs
Bank 6
High-Speed IOEs