HC230F1020 Altera, HC230F1020 Datasheet - Page 219

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Stratix II ALM
Adaptation into
HardCopy II
Logic
Altera Corporation
September 2008
Table 8–19
The basic logic building block in the Stratix II architecture is the ALM.
Each ALM contains a variety of look-up table- (LUT-) based resources,
two programmable registers, two dedicated full adders, and various
routing resources to and from the ALM.
HardCopy II devices do not have ALM blocks, but use a fine-grain
architecture called HCells. HCells can implement all combinations of
Stratix II ALM and DSP logic. Each HardCopy II companion device
contains an abundance of HCells to implement a Stratix II design
utilizing all available ALMs. Therefore, there are no compatibility
constraints when compiling for HardCopy II devices.
When compiling a Stratix II design into a HardCopy II companion
device, the Quartus II software replaces ALM blocks used in Stratix II
with predefined HCell macros. Unused ALM resources are not
implemented in HardCopy II devices. This allows for optimal placement
of the HardCopy II floor plan and significant power savings.
Figure 8–6
using only one of the registers. When compiling this Stratix II design for
a HardCopy II companion device, the Quartus II compiler replaces the
Number of unique clock sources in the
Table 8–19. Clock Network Resources and Features Available in HardCopy II
Devices
Number of unique clock sources in a
Number of regional clock networks
Number of global clock networks
Clocking regions for high fan-out
Regional clock input sources
Global clock input sources
Resources and Features
Power-down mode
lists the clock resources available in HardCopy II devices.
shows an example of a Stratix II ALM block implementation
entire device
applications
quadrant
Stratix II ALM Adaptation into HardCopy II Logic
Quadrant region, dual-regional, entire
48 (16 global clocks and 32 regional
Global and regional clock networks,
Clock input pins, PLL outputs, logic
Clock input pins, PLL outputs, logic
24 (16 global clocks and 8 regional
device via global or regional clock
dual-regional clock region
Availability
networks
clocks)
clocks)
array
array
16
32
Preliminary
8–31