HC230F1020 Altera, HC230F1020 Datasheet - Page 5

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
Notes to
(1)
(2)
(3)
(4)
(5)
ASIC equivalent gates
M4K RAM blocks
(4 Kbits plus parity)
M-RAM blocks
(512 Kbits plus parity)
Total RAM bits
(including parity bits)
Enhanced PLLs
Fast PLLs
Maximum user I/O pins (4),
Table 1–1. HardCopy II Device Family Features
HC210W devices are in a wire bond package. All other HardCopy II devices and Stratix II FPGAs use a flip-chip
package. Devices in a wire bond package offer different performance and signal integrity characteristics compared
to devices in a flip-chip package.
This is the number of ASIC equivalent gates available in the HardCopy II base array, shared between both adaptive
logic module (ALM) logic and DSP functions from a Stratix II FPGA prototype. Each Stratix II adaptive logic
module (ALM) is equal to approximately 30 ASIC equivalent gates. The number of ASIC equivalent gates usable
is bounded by the number of ALMs in the companion Stratix II FPGA device.
Total number of usable M4K blocks is 768, which allows migration compatibility when prototyping with an
EP2S180 device. This may be different from the Quartus II software total physical M4K count of the HC240.
The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs.
The Quartus II I/O pin counts include an additional pin (PLLENA), which is not available as a general-purpose I/O
pin. The PLLENA pin can only be used to enable the PLLs.
Table
Feature
1–1:
(2)
(5)
The HardCopy II device family consists of five devices.
summarizes the features available in the HardCopy II devices.
HC210W
1,000,000
875,520
190
308
0
2
2
(1)
1,000,000
875,520
HC210
190
334
0
2
2
1,900,000
3,059,712
HC220
408
494
2
2
2
2,900,000
6,368,256
HC230
614
698
4
6
4
Feature Overview
Table 1–1
3,600,000
8,847,360
Preliminary
768
HC240
951
9
4
8
(3)
1–3