HC230F1020 Altera, HC230F1020 Datasheet - Page 166

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
7–2
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HardCopy II versus Stratix II Timing
The back-end design of your HardCopy II structured ASIC includes
timing closure in accordance with the timing specification achieved in the
Quartus II software for the Stratix II FPGA prototype and HardCopy II
device. However, you should be aware that this does not mean that actual
path timing in the Stratix II FPGA is duplicated in the HardCopy II
device. In fact, because of the architectural differences between Stratix II
and HardCopy II devices, you should expect that while internal and I/O
path timing are within whatever timing constraints you applied, actual
path delays are different.
The key factors that impact timing differences between Stratix II and
HardCopy II devices are listed below.
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The following sections briefly describe the effect of these factors on
HardCopy II timing characteristics.
Internal Register-to-Register Timing
Internal timing is the timing of paths from register to register within core
logic. Internal timing is dependent on the transport delays of logic
elements on register-to-register paths and the overall effects of parasitic
capacitance, parasitic resistance, and crosstalk on routing connections
between those logic elements.
User-logic implementation in HardCopy II devices is more area efficient
and often has improved timing when compared with the Stratix II FPGA.
These advantages are the result of re-mapping the coarse-grain,
An explanation of the use of timing constraints in the Quartus II
software, including some of the important timing-related checks
reported by the HardCopy II Advisor and Design Assistant
Timing constraint recommendations for your HardCopy II project
and recommendations for handling legacy designs that use timing
constraints not supported in the HardCopy II design flow
The HardCopy II die is significantly smaller than its Stratix II
counterpart
Coarse-grain adaptive logic modules (ALMs) in Stratix II devices are
mapped to fine-grain HCell macros in HardCopy II devices
Design connections are implemented using custom metal routing in
HardCopy II devices
HardCopy II devices contain no SRAM-configurable programmable
connection points
Leaf sub-trees in HardCopy II global clock networks are custom
routed
Altera Corporation
September 2008