HC230F1020 Altera, HC230F1020 Datasheet - Page 7

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Document
Revision History
Altera Corporation
September 2008
Notes to
(1)
(2)
(3)
Package
Type
Dimension
Pitch (mm)
Area (mm
Length × width
(mm × mm)
Device
HC210W
HC210
HC220
HC230
HC240
Date and Document
September 2008,
v2.6
June 2007, v2.5
Table 1–3. HardCopy II Package Options and I/O Pin Counts
Table 1–4. Document Revision History (Part 1 of 2)
The Quartus II I/O pin counts include an additional pin (PLLENA) which is not available as a general-purpose I/O
pin. The PLLENA pin can only be used to enable the PLLs.
The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs.
The EP2S90 FPGA prototype uses a 484-pin hybrid FineLine BGA package. For more information, refer to the
Stratix II Device Handbook.
Version
Table
2
)
1–3:
FineLine BGA
Wire bond
484-Pin
23 × 23
1.00
Updated chapter number and metadata.
Minor text edits.
529
308
(3)
HardCopy II devices are available in the packages shown in
Table 1–4
FineLine BGA
Flip-chip
484-Pin
23 × 23
1.00
529
334
(3)
shows the revision history for this chapter.
Changes Made
FineLine BGA
Maximum User I/O Pins
Flip-chip
672-Pin
27 × 27
1.00
729
492
FineLine BGA
Notes
Flip-chip
780-Pin
29 × 29
1.00
841
494
(1),
(2)
FineLine BGA
Document Revision History
1,020-Pin
Flip-chip
33 × 33
1,089
1.00
698
742
Summary of Changes
—
—
FineLine BGA
Table
1,508-Pin
Preliminary
Flip-chip
40 × 40
1,600
1.00
951
1–3.
1–5