HC230F1020 Altera, HC230F1020 Datasheet - Page 156

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
Understanding
Report Files
6–28
<revision>.map.rpt
<revision>.map.eqn Analysis & Synthesis
<revision>.fit.rpt
<revision>.fit.eqn
<revision>.drc.rpt
Table 6–9. Stratix II Compile Report File Descriptions
Switch
f
Analysis & Synthesis
Fitter
Fitter
Design Assistant
This command initializes the database for the HardCopy II revision and
creates a new QSF file (in this example, demo_design_hcii.qsf), ensuring
that all constraints for the Stratix II FPGA revision are ported over.
Next, the current working revision for the Quartus II project is changed
to the HardCopy II revision and the design is compiled for the
HardCopy II device target:
tcl> set_current_revision demo_design_hcii
tcl> execute_flow -compile
As with the prototype Stratix II revision, report files are generated in the
project directory for each of the tools that are executed.
The execute_flow command generates a number of report files in the
project directory. These files summarize messages displayed on the
console during compilation and provide additional information about
the design. The name of each report file follows the format
<revision><tool short name>.summary and <revision><tool short name>.rpt,
where <revision> is the revision name of the current design. The
.summary file contains a brief summary of messages and results from the
tool while the .rpt file contains more detailed messages and information.
For a HardCopy II project, two sets of report files are generated: one for
the Stratix II prototype FPGA revision and one for the HardCopy II
revision.
1
For more information on customizing and managing report files, refer to
the Tcl Packages and Commands report section of the Quartus II Tcl
Reference Manual.
Tool
The Tcl report package provides a powerful collection of
procedures for customizing and managing report files related to
the Quartus II fitter and timing analysis engines.
Table 6–9
Synthesis settings, source files, messages, and resource usage.
Implementation equations and device resource instantiations.
Fitter settings, layout optimizations, resources, pin-out, and
messages.
Implemented equations and device resource instantiations after
fitting.
Design rule settings, violations, and messages.
describes the different report files.
(Part 1 of 2)
Description
Altera Corporation
September 2008