HC230F1020 Altera, HC230F1020 Datasheet - Page 4

no-image

HC230F1020

Manufacturer Part Number
HC230F1020
Description
Manufacturer
Altera
Datasheet

Specifications of HC230F1020

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HC230F1020
Manufacturer:
ALTERA
0
Part Number:
HC230F1020AJ
Manufacturer:
ALTERA
0
Part Number:
HC230F1020ANQ
Manufacturer:
Discera
Quantity:
2 000
Part Number:
HC230F1020AW
Manufacturer:
ALTERA
0
Part Number:
HC230F1020BA
Manufacturer:
ALTERA
0
Part Number:
HC230F1020BL
Manufacturer:
ALTERA
0
HardCopy Series Handbook, Volume 1
1–2
Preliminary
1
System performance up to 350 MHz
Up to 50% power reduction (dynamic and static) for typical designs
compared to Stratix II FPGA prototypes
Internal Memory
Phase-Locked Loops (PLLs)
I/O Standards and Intellectual Property (IP)
Packaging
The actual performance and power consumption improvements
mentioned in this datasheet are design-dependent.
Up to 8,847,360 RAM bits available (including parity bits)
True dual-port memory, suitable for use in first-in-first-out
(FIFO) buffers
Up to 16 global clocks with 24 clocking resources per device
region
Clock control block supports dynamic clock network
enable/disable and dynamic global clock network source
selection
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per
device which provide identical features as the FPGA
counterparts, including spread spectrum, programmable
bandwidth, clock switchover, real-time PLL reconfiguration,
advanced multiplication, and phase shifting
Support for numerous single-ended and differential I/O
standards such as LVTTL, LVCMOS, PCI, PCI-X, SSTL, HSTL,
and LVDS
High-speed differential I/O support on up to 116 channels with
dynamic phase alignment (DPA) circuitry for
1-Gigabit-per-second (Gbps) performance
Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
Support for high-speed external memory, including DDR and
DDR2 SDRAM, RLDRAM II, QDRII SRAM, and SDR SDRAM
Support for multiple intellectual property megafunctions from
Altera MegaCore
Program (AMPP
Pin-compatible with Stratix II FPGA prototypes
Up to 951 user I/O pins available
Available in wire bond and flip-chip space-saving
FineLine BGA packages
SM
®
functions, and Altera Megafunction Partners
) megafunctions
(Table
1–3).
Altera Corporation
September 2008

Related parts for HC230F1020