HC230F1020 Altera, HC230F1020 Datasheet - Page 179

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
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make the design fully constrained, and use the same constraints for both
FPGA and HardCopy revisions in the flow. If you do not do this, you
cannot determine whether the HardCopy series device meets the
required timing of the end target system. The SDC format timing
constraints can be generated using the Quartus II SDC File Editor which
provides line numbering, syntax coloring, and call tips. You can enter
timing constraints and exceptions directly or specify them from the
Constraints menu. An example of the SDC commands is shown in the
following section.
The following constraints must be included:
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For information on the SDC editor, refer to the TimeQuest Timing Analyzer
chapter in volume 3 of the Quartus II Handbook.
For more information on timing constraints for the TimeQuest timing
analyzer, refer to the TimeQuest Timing Analyzer chapter in volume 3 of
the Quartus II Handbook.
For more information on timing assignments for Classic Timing
Analyzer, refer to the Classic Timing Analyzer chapter in volume 3 of the
Quartus II Handbook.
Clock Definitions
You can use these definitions to describe the parameters of all different
clock domains in a design. Clock parameters that must be defined are
frequency, time at which the clock edge rises, time at which the clock edge
falls, clock uncertainty (for example: jitter, noise, and designed in timing
margin), and clock name.
Clock definitions
Primary input port timing
Primary output port timing
Combinational timing
Timing exceptions
Constraining Timing of HardCopy Series Devices
Figure 7–7
illustrates the attributes.
7–15