PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 130

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
Table 11-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 26.0 “Electrical Characteristics” for more
details.
TABLE 11-2:
11.1.3
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level
without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU and RJPU (PORTG<7:5>) for the other ports.
11.1.4
The output pins for several peripherals are also
equipped with a configurable open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. The option is selectively enabled by
setting the open-drain control bit for the corresponding
module in TRISG and LATG. Their configuration is
discussed in more detail in the sections for PORTC,
PORTE and PORTG.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
(Figure 11-2). When a digital logic high signal is output,
it is pulled up to the higher voltage level.
DS39774D-page 130
PORTA<5:0>
PORTF
PORTG
PORTH
Note 1:
Low
(1)
Not available on 64-pin devices.
PULL-UP CONFIGURATION
OPEN-DRAIN OUTPUTS
OUTPUT DRIVE LEVELS FOR
VARIOUS PORTS
PORTD
PORTE
PORTJ
Medium
(1)
PORTC
PORTA<7:6>
PORTB
High
FIGURE 11-2:
11.2
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISA and LATA.
RA4/T0CKI is a Schmitt Trigger input. All other PORTA
pins have TTL input levels and full CMOS output drivers.
The RA4 pin is multiplexed with the Timer0 clock input.
RA5 and RA<3:0> are multiplexed with analog inputs
for the A/D Converter.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the PCFG<3:0>
control bits in the ADCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
RA6/OSC2/CLKO
serve as the external circuit connections for the exter-
nal (primary) oscillator circuit (HS Oscillator modes), or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use INTOSC or INTRC as the default oscillator mode
(FOSC2 Configuration bit is ‘0’), RA6 and RA7 are
automatically configured as digital I/O; the oscillator
and clock in/clock out functions are disabled.
EXAMPLE 11-1:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
Note:
3.3V
PORTA, TRISA and LATA Registers
PORTA
LATA
07h
ADCON1 ; for digital inputs
0BFh
TRISA
RA5 and RA<3:0> are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
V
DD
PIC18F85J11
(at logic ‘1’)
; Initialize PORTA by
; clearing output latches
; Alternate method to
; clear output data latches
; Configure A/D
; Value used to initialize
; data direction
; Set RA<7, 5:0> as inputs,
; RA<6> as output
and
USING THE OPEN-DRAIN
OUTPUT (USARTs
SHOWN AS EXAMPLES
INITIALIZING PORTA
 2010 Microchip Technology Inc.
TX
RA7/OSC1/CLKI
X
3.3V
+5V
normally
5V