PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 242

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

Synchronous Master mode in that the shift clock is sup-
PIC18F85J11 FAMILY
18.5
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
plied externally at the CK1 pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
18.5.1
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG1 and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 18-9:
DS39774D-page 242
INTCON
PIR1
PIE1
IPR1
RCSTA1
TXREG1
TXSTA1
BAUDCON1 ABDOVF
SPBRGH1
SPBRG1
LATG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREG1
register.
Flag bit, TX1IF, will not be set.
When the first word has been shifted out of TSR,
the TXREG1 register will transfer the second
word to the TSR and flag bit, TX1IF, will now be
set.
If enable bit, TX1IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
EUSART Synchronous Slave Mode
EUSART SYNCHRONOUS SLAVE
TRANSMIT
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
PSPIE
PSPIP
PSPIF
CSRC
SPEN
U2OD
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
RCIDL
U1OD
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
TMR0IE
RXDTP
RC1IF
RC1IE
RC1IP
SREN
TXEN
Bit 5
—
TXCKP
INT0IE
LATG4
CREN
TX1IF
TX1IE
TX1IP
SYNC
Bit 4
ADDEN
SENDB
BRG16
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
LATG3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TX1IE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG1 register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
LATG2
BRGH
FERR
Bit 2
—
—
—
—
TMR2IF
TMR2IE
TMR2IP
INT0IF
LATG1
OERR
TRMT
 2010 Microchip Technology Inc.
WUE
Bit 1
TMR1IF
TMR1IE
TMR1IP
ABDEN
LATG0
RX9D
TX9D
RBIF
Bit 0
on page
Values
Reset
57
59
59
59
59
59
59
60
60
59
60