PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 245

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

19.0
The Addressable Universal Synchronous Asynchro-
nous Receiver Transmitter (AUSART) module is very
similar in function to the Enhanced USART module
discussed in the previous chapter. It is provided as an
additional channel for serial communication with
external devices for those situations that do not require
Auto-Baud Detection or LIN/J2602 bus support.
The AUSART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The pins of the AUSART module are multiplexed with
the
RG2/RX2/DT2, respectively). In order to configure
these pins as an AUSART:
• SPEN bit (RCSTA2<7>) must be set (= 1)
• TRISG<2> bit must be set (= 1)
• TRISG<1> bit must be cleared (= 0) for
• TRISG<1> bit must be set (= 1) for Synchronous
 2010 Microchip Technology Inc.
Asynchronous and Synchronous Master modes
Slave mode
functions
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
of
PORTG
(RG1/TX2/CK2
and
PIC18F85J11 FAMILY
The driver for the TX2 output pin can also be optionally
configured as an open-drain output. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the U2OD
bit (LATG<7>). Setting this bit configures the pin for
open-drain operation.
19.1
The operation of the Addressable USART module is
controlled through two
RCSTA2. These are detailed in Register 19-1 and
Register 19-2, respectively.
Note:
Control Registers
The AUSART control will automatically
reconfigure the pin from input to output as
needed.
registers,
DS39774D-page 245
TXSTA2
and