PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 402

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
PWM (CCP Module)
Q
Q Clock ............................................................................ 176
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 49
RC_RUN Mode .................................................................. 46
RCALL .............................................................................. 329
RCON Register
Reader Response ............................................................ 406
Register File ....................................................................... 75
Register File Summary ................................................. 77–80
Registers
DS39774D-page 402
Associated Registers ............................................... 177
Duty Cycle ................................................................ 176
Example Frequencies/Resolutions .......................... 176
Period ....................................................................... 175
Setup for PWM Operation ........................................ 177
TMR2 to PR2 Match ................................................ 175
Bit Status During Initialization .................................... 56
ADCON0 (A/D Control 0) ......................................... 259
ADCON1 (A/D Control 1) ......................................... 260
ADCON2 (A/D Control 2) ......................................... 261
BAUDCON1 (Baud Rate Control 1) ......................... 226
CCPxCON (CCPx Control) ...................................... 169
CMCON (Comparator Control) ................................ 269
CONFIG1H (Configuration 1 High) .......................... 281
CONFIG1L (Configuration 1 Low) ............................ 281
CONFIG2H (Configuration 2 High) .......................... 283
CONFIG2L (Configuration 2 Low) ............................ 282
CONFIG3H (Configuration 3 High) .......................... 284
CONFIG3L (Configuration 3 Low) ...................... 65, 284
CVRCON (Comparator Voltage
DEVID1 (Device ID Register 1) ................................ 285
DEVID2 (Device ID Register 2) ................................ 285
EECON1 (EEPROM Control 1) .................................. 91
INTCON (Interrupt Control) ...................................... 115
INTCON2 (Interrupt Control 2) ................................. 116
INTCON3 (Interrupt Control 3) ................................. 117
IPR1 (Peripheral Interrupt Priority 1) ........................ 124
IPR2 (Peripheral Interrupt Priority 2) ........................ 125
IPR3 (Peripheral Interrupt Priority 3) ........................ 126
MEMCON (External Memory Bus Control) .............. 100
OSCCON (Oscillator Control) .................................... 36
OSCTUNE (Oscillator Tuning) ................................... 37
PIE1 (Peripheral Interrupt Enable 1) ........................ 121
PIE2 (Peripheral Interrupt Enable 2) ........................ 122
PIE3 (Peripheral Interrupt Enable 3) ........................ 123
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 118
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 119
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 120
PSPCON (Parallel Slave Port Control) .................... 151
RCON (Reset Control) ....................................... 52, 127
RCSTA1 (EUSART Receive Status
RCSTA2 (AUSART Receive Status
SSPCON1 (MSSP Control 1, I
SSPCON1 (MSSP Control 1, SPI Mode) ................. 181
SSPCON2 (MSSP Control 2, I
SSPCON2 (MSSP Control 2, I
SSPSTAT (MSSP Status, I
SSPSTAT (MSSP Status, SPI Mode) ...................... 180
Reference Control) ........................................... 275
and Control) ..................................................... 225
and Control) ..................................................... 247
2
C Mode) ....................... 189
2
2
2
C Mode) ................. 190
C Master Mode) ..... 191
C Slave Mode) ....... 192
RESET ............................................................................. 329
Reset ................................................................................. 51
Resets .............................................................................. 279
RETFIE ............................................................................ 330
RETLW ............................................................................ 330
RETURN .......................................................................... 331
Return Address Stack ........................................................ 67
Return Stack Pointer (STKPTR) ........................................ 68
Revision History ............................................................... 393
RLCF ............................................................................... 331
RLNCF ............................................................................. 332
RRCF ............................................................................... 332
RRNCF ............................................................................ 333
S
SCK ................................................................................. 179
SDI ................................................................................... 179
SDO ................................................................................. 179
SEC_IDLE Mode ............................................................... 48
SEC_RUN Mode ................................................................ 44
Serial Clock, SCK ............................................................ 179
Serial Data In (SDI) .......................................................... 179
Serial Data Out (SDO) ..................................................... 179
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 333
Slave Select (SS) ............................................................. 179
SLEEP ............................................................................. 334
Sleep
Software Simulator (MPLAB SIM) ................................... 297
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 279
SPI Mode (MSSP)
STATUS .................................................................... 81
STKPTR (Stack Pointer) ............................................ 68
T0CON (Timer0 Control) ......................................... 153
T1CON (Timer1 Control) ......................................... 157
T2CON (Timer2 Control) ......................................... 163
T3CON (Timer3 Control) ......................................... 165
TXSTA1 (EUSART Transmit Status
TXSTA2 (AUSART Transmit Status
WDTCON (Watchdog Timer Control) ...................... 287
Brown-out Reset (BOR) ............................................. 51
MCLR Reset, During Power-Managed Modes .......... 51
MCLR Reset, Normal Operation ................................ 51
Power-on Reset (POR) .............................................. 51
RESET Instruction ..................................................... 51
Stack Full Reset ......................................................... 51
Stack Underflow Reset .............................................. 51
Watchdog Timer (WDT) Reset .................................. 51
Brown-out Reset (BOR) ........................................... 279
Oscillator Start-up Timer (OST) ............................... 279
Power-on Reset (POR) ............................................ 279
Power-up Timer (PWRT) ......................................... 279
OSC1 and OSC2 Pin States ...................................... 42
Associated Registers ............................................... 187
Bus Mode Compatibility ........................................... 187
Effects of a Reset .................................................... 187
Enabling SPI I/O ...................................................... 183
Master Mode ............................................................ 184
Master/Slave Connection ......................................... 183
Operation ................................................................. 182
Operation in Power-Managed Modes ...................... 187
Serial Clock .............................................................. 179
Serial Data In ........................................................... 179
and Control) ..................................................... 224
and Control) ..................................................... 246
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