PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 131

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

TABLE 11-3:
TABLE 11-4:
 2010 Microchip Technology Inc.
RA0/AN0
RA1/AN1
RA2/AN2/V
RA3/AN3/
V
RA4/T0CKI
RA5/AN4
RA6/OSC2/
CLKO
RA7/OSC1/
CLKI
Legend:
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PORTA
LATA
TRISA
ADCON1
Legend: — = Unimplemented, read as ‘0’, x = Don’t care. Shaded cells are not used by PORTA.
Note 1:
REF
Name
Pin Name
+
REF
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins,
they are disabled and read as ‘x’.
TRISA7
LATA7
-
RA7
Bit 7
—
Function
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
PORTA FUNCTIONS
T0CKI
V
OSC2
CLKO
OSC1
(1)
V
CLKI
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
RA7
(1)
REF
REF
(1)
+
-
TRISA6
LATA6
RA6
Bit 6
—
Setting
TRIS
(1)
0
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
x
0
1
1
0
1
x
x
0
1
x
x
(1)
(1)
TRISA5
VCFG1
LATA5
I/O
Bit 5
O
O
O
O
O
O
O
O
O
O
RA5
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
TTL
DIG
DIG
TTL
I/O
ST
ST
TRISA4
VCFG0
LATA4
Bit 4
RA4
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
LATA<2> data output; not affected by analog input.
PORTA<2> data input. Disabled when analog functions enabled.
A/D Input Channel 2. Default input configuration on POR.
A/D and comparator low reference voltage input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D Input Channel 3. Default input configuration on POR.
A/D and comparator high reference voltage input.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D Input Channel 4. Default configuration on POR.
LATA<6> data output; disabled when FOSC2 Configuration bit is set.
PORTA<6> data input; disabled when FOSC2 Configuration bit is set.
Main oscillator feedback output connection (HS and HSPLL modes).
System cycle clock output, F
LATA<7> data output; disabled when FOSC2 Configuration bit is set.
PORTA<7> data input; disabled when FOSC2 Configuration bit is set.
Main oscillator input connection (HS and HSPLL modes).
Main external clock source input (EC and ECPLL modes).
PIC18F85J11 FAMILY
TRISA3
PCFG3
LATA3
Bit 3
RA3
TRISA2
PCFG2
LATA2
Bit 2
RA2
OSC
Description
/4 (EC and ECPLL modes).
TRISA1
PCFG1
LATA1
Bit 1
RA1
TRISA0
PCFG0
LATA0
Bit 0
RA0
DS39774D-page 131
on page
Values
Reset
60
60
60
59