PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 188

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
17.4
The MSSP module in I
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial Clock (SCL) – RC3/SCK/SCL
• Serial Data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs by setting
the TRISC<4:3> bits.
FIGURE 17-7:
DS39774D-page 188
Note:
SCL
SDA
I
2
C Mode
Disabling the MSSP module by clearing
the SSPEN (SSPCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPSTAT, SSPCON1 and
SSPCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
Read
Shift
Clock
MSb
Address Mask
Stop bit Detect
Match Detect
SSPADD reg
MSSP BLOCK DIAGRAM
(I
SSPBUF reg
SSPSR reg
Start and
2
2
C mode fully implements all
C™ MODE)
LSb
Write
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
Internal
Data Bus
17.4.1
The MSSP module has six registers for I
These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPSR) – Not directly
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
Many of the bits in SSPCON2 assume different
functions, depending on whether the module is operat-
ing in Master or Slave mode; SSPCON2<5:2> bits also
assume different names in Slave mode. The different
aspects of SSPCON2 are shown in Register 17-5 (for
Master mode) and Register 17-6 (Slave mode).
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address when
the MSSP is configured in I
MSSP is configured in Master mode, the lower seven
bits of SSPADD act as the Baud Rate Generator reload
value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
(SSPBUF)
accessible
transmission,
REGISTERS
 2010 Microchip Technology Inc.
the
2
2
C mode operation. The
C Slave mode. When the
SSPBUF
2
C operation.
is
not