PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 146

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
TABLE 11-15: PORTG FUNCTIONS
TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
DS39774D-page 146
RG0
RG1/TX2/CK2
RG2/RX2/DT2
RG3
RG4
Legend:
PORTG
LATG
TRISG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1:
Pin Name
Name
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port
direction or is overridden for this option).
Unimplemented on 64-pin devices, read as ‘0’.
Function
SPIOD
RDPU
RG0
RG2
RG3
RG4
U2OD
CK2
RX2
DT2
R21
TX2
Bit 7
Setting
CCP2OD CCP1OD
TRIS
REPU
U1OD
0
1
0
1
1
1
1
0
1
1
1
1
0
1
0
1
Bit 6
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
RJPU
Bit 5
—
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
(1)
ST
ST
ST
ST
ST
ST
ST
ST
TRISG4
LATG4
LATG<0> data output.
PORTG<0> data input.
LATG<1> data output.
PORTG<1> data input.
Synchronous serial data output (AUSART2 module); takes priority over
port data.
Synchronous serial data input (AUSART2 module). User must configure
as an input.
Synchronous serial clock input (AUSART2 module).
LATG<2> data output.
PORTG<2> data input.
Asynchronous serial receive data input (AUSART2 module).
Synchronous serial data output (AUSART2 module); takes priority over
port data.
Synchronous serial data input (AUSART2 module). User must configure
as an input.
LATG<3> data output.
PORTG<3> data input.
LATG<4> data output.
PORTG<4> data input.
Bit 4
RG4
TRISG3
LATG3
Bit 3
RG3
TRISG2
LATG2
Bit 2
RG2
Description
TRISG1
LATG1
Bit 1
RG1
 2010 Microchip Technology Inc.
TRISG0
LATG0
Bit 0
RG0
Values on
Reset
page
60
60
60