PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 147

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

11.9
PORTH is an 8-bit wide, bidirectional I/O port. The corre-
sponding Data Direction and Output Latch registers are
TRISH and LATH. All pins are digital only and tolerate
voltages up to 5.5V.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the external memory interface is enabled, four of
the PORTH pins function as the high-order address
lines for the interface. The address output from the
interface takes priority over other digital I/O. The
corresponding TRISH bits are also overridden.
TABLE 11-17: PORTH FUNCTIONS
TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
 2010 Microchip Technology Inc.
RH0/A16
RH1/A17
RH2/A18
RH3/A19
RH4
RH5
RH6
RH7
Legend:
PORTH
LATH
TRISH
Note:
Pin Name
Name
PORTH, LATH and TRISH Registers
PORTH is available only on 80-pin
devices.
direction or is overridden for this option).
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port
TRISH7
LATH7
Function
Bit 7
RH7
RH0
RH1
RH2
RH3
RH4
RH5
RH6
RH7
A16
A17
A18
A19
Setting
TRISH6
LATH6
TRIS
Bit 6
RH6
0
1
x
0
1
x
0
1
x
0
1
x
0
1
0
1
0
1
0
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
TRISH5
LATH5
Bit 5
RH5
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
LATH<0> data output.
PORTH<0> data input.
External memory interface, Address Line 16. Takes priority over port data.
LATH<1> data output.
PORTH<1> data input.
External memory interface, Address Line 17. Takes priority over port data.
LATH<2> data output.
PORTH<2> data input.
External memory interface, Address Line 18. Takes priority over port data.
LATH<3> data output.
PORTH<3> data input.
External memory interface, Address Line 19. Takes priority over port data.
LATH<4> data output.
PORTH<4> data input.
LATH<5> data output.
PORTH<5> data input.
LATH<6> data output.
PORTH<6> data input.
LATH<7> data output.
PORTH<7> data input.
TRISH4
LATH4
Bit 4
RH4
PIC18F85J11 FAMILY
TRISH3
LATH3
EXAMPLE 11-8:
Bit 3
RH3
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
TRISH2
PORTH
LATH
0Fh
ADCON1
0CFh
TRISH
LATH2
Bit 2
RH2
Description
TRISH1
LATH1
INITIALIZING PORTH
Bit 1
RH1
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure PORTH as
; digital I/O
; Value used to
; initialize data
; direction
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
TRISH0
LATH0
Bit 0
RH0
DS39774D-page 147
on page
Values
Reset
60
60
60