PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 403

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

SS .................................................................................... 179
SSPOV ............................................................................. 213
SSPOV Status Flag ......................................................... 213
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 69
STATUS Register .............................................................. 81
SUBFSR .......................................................................... 345
SUBFWB .......................................................................... 334
SUBLW ............................................................................ 335
SUBULNK ........................................................................ 345
SUBWF ............................................................................ 335
SUBWFB .......................................................................... 336
SWAPF ............................................................................ 336
T
Table Pointer Operations (table) ........................................ 92
Table Reads/Table Writes ................................................. 69
TBLRD ............................................................................. 337
TBLWT ............................................................................. 338
Timer0 .............................................................................. 153
Timer1 .............................................................................. 157
Timer2 .............................................................................. 163
Timer3 .............................................................................. 165
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Serial Data Out ........................................................ 179
Slave Mode .............................................................. 185
Slave Select ............................................................. 179
Slave Select Synchronization .................................. 185
SPI Clock ................................................................. 184
Typical Connection .................................................. 183
R/W Bit ............................................................. 193, 195
Associated Registers ............................................... 155
Clock Source Select (T0CS Bit) ............................... 154
Interrupt .................................................................... 155
Operation ................................................................. 154
Prescaler .................................................................. 155
Prescaler Assignment (PSA Bit) .............................. 155
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 155
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 154
Source Edge Select (T0SE Bit) ................................ 154
16-Bit Read/Write Mode ........................................... 159
Associated Registers ............................................... 161
Interrupt .................................................................... 160
Operation ................................................................. 158
Oscillator .......................................................... 157, 159
Overflow Interrupt .................................................... 157
Resetting, Using the CCPx Special
TMR1H Register ...................................................... 157
TMR1L Register ....................................................... 157
Use as a Clock Source ............................................ 159
Use as a Real-Time Clock ....................................... 160
Associated Registers ............................................... 164
Interrupt .................................................................... 164
Operation ................................................................. 163
Output ...................................................................... 164
PR2 Register ............................................................ 175
TMR2 to PR2 Match Interrupt .................................. 175
16-Bit Read/Write Mode ........................................... 167
Associated Registers ............................................... 167
Interrupt .................................................................... 167
Operation ................................................................. 166
Oscillator .......................................................... 165, 167
Overflow Interrupt .................................................... 165
Switching Assignment ...................................... 155
Layout Considerations ..................................... 160
Event Trigger ................................................... 160
PIC18F85J11 FAMILY
Timing Diagrams
Special Event Trigger (CCP) ................................... 167
TMR3H Register ...................................................... 165
TMR3L Register ...................................................... 165
A/D Conversion ....................................................... 385
Acknowledge Sequence .......................................... 216
Asynchronous Reception ................................. 236, 253
Asynchronous Transmission ........................... 234, 251
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 232
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 237
Baud Rate Generator with Clock Arbitration ............ 210
BRG Overflow Sequence ........................................ 232
BRG Reset Due to SDA Arbitration During
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition (SCL = 0) .... 219
Bus Collision During a Stop Condition (Case 1) ...... 221
Bus Collision During a Stop Condition (Case 2) ...... 221
Bus Collision During Start Condition (SDA Only) .... 218
Bus Collision for Transmit and Acknowledge .......... 217
Capture/Compare/PWM (CCP1, CCP2) .................. 374
CLKO and I/O .......................................................... 368
Clock Synchronization ............................................. 203
Clock/Instruction Cycle .............................................. 70
EUSART/AUSART Synchronous
EUSART/AUSART Synchronous
Example SPI Master Mode (CKE = 0) ..................... 375
Example SPI Master Mode (CKE = 1) ..................... 376
Example SPI Slave Mode (CKE = 0) ....................... 377
Example SPI Slave Mode (CKE = 1) ....................... 378
External Clock (All Modes Except PLL) ................... 366
External Memory Bus for Sleep
External Memory Bus for TBLRD
Fail-Safe Clock Monitor ........................................... 292
First Start Bit Timing ................................................ 211
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MSSP I
MSSP I
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C Bus Data ............................................................ 380
C Bus Start/Stop Bits ............................................ 379
C Master Mode (7 or 10-Bit Transmission) ........... 214
C Master Mode (7-Bit Reception) ......................... 215
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) .......... 199
C Slave Mode (10-Bit Reception, SEN = 1) .......... 205
C Slave Mode (10-Bit Transmission) .................... 201
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............ 196
C Slave Mode (7-Bit Reception, SEN = 1) ............ 204
C Slave Mode (7-Bit Transmission) ...................... 198
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 216
(Back-to-Back) ......................................... 234, 251
Normal Operation ............................................ 237
Start Condition ................................................. 219
Condition (Case 1) ........................................... 220
Condition (Case 2) ........................................... 220
Receive (Master/Slave) ................................... 383
Transmission (Master/Slave) ........................... 383
(Extended Microcontroller Mode) ............ 106, 108
(Extended Microcontroller Mode) ............ 106, 108
ADMSK = 01001) ............................................ 200
ADMSK = 01011) ............................................ 197
Sequence (7 or 10-Bit Addressing Mode) ....... 206
2
2
C Bus Data ................................................ 381
C Bus Start/Stop Bits ................................. 381
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