PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 385
PIC18F64J11T-I/PT
Manufacturer Part Number
PIC18F64J11T-I/PT
Description
16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(408 pages)
3.PIC18F63J11-IPT.pdf
(4 pages)
4.PIC18F63J11-IPT.pdf
(36 pages)
5.PIC18F63J11-IPT.pdf
(10 pages)
6.PIC18F63J11-IPT.pdf
(6 pages)
Specifications of PIC18F64J11T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18F64J11T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F64J11T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F63J11-IPT PDF datasheet #3
- PIC18F63J11-IPT PDF datasheet #4
- PIC18F63J11-IPT PDF datasheet #5
- PIC18F63J11-IPT PDF datasheet #6
- Current page: 385 of 408
- Download datasheet (4Mb)
FIGURE 26-23:
TABLE 26-26: A/D CONVERSION REQUIREMENTS
2010 Microchip Technology Inc.
130
131
132
135
137
Note 1:
Param
No.
Note 1:
A/D DATA
SAMPLE
2:
3:
4:
A/D CLK
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
DIS
2:
GO
The time of the A/D clock period is dependent on the device frequency and the T
ADRES registers may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
Q4
If the A/D clock source is selected as RC, a time of T
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D Clock Period
Conversion Time
(not including acquisition time)
Acquisition Time
Switching Time from Convert Sample
Discharge Time
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
9
(3)
to V
SS
8
or V
OLD_DATA
7
SS
(2)
to V
SAMPLING STOPPED
. . .
CY
DD
is added before the A/D clock starts. This allows the SLEEP instruction
). The source impedance (R
CY
. . .
130
131
PIC18F85J11 FAMILY
cycle.
Min
0.7
1.4
0.2
—
11
—
2
(Note 4)
25.0
Max
12
—
—
—
1
1
(1)
Units
T
µs
µs
µs
µs
AD
0
S
) on the input channels is 50.
T
A/D RC mode
-40C to +85C
OSC
AD
based, V
clock divider.
DONE
NEW_DATA
Conditions
DS39774D-page 385
T
CY
(Note 1)
REF
3.0V
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