HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 10

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.0
Intel
Datasheet
10
®
5100 Memory Controller Hub Chipset
4.6
Functional Description ........................................................................................... 278
5.1
5.2
5.3
5.4
5.5
4.5.2
4.5.3
Configuration Space ......................................................................................... 277
Processor Front Side Buses ............................................................................... 278
5.1.1
5.1.2
5.1.3
System Memory Controller ................................................................................ 280
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10 Normal Self-refresh Entry ...................................................................... 290
Interrupts ....................................................................................................... 291
XAPIC Interrupt Message Delivery...................................................................... 291
5.4.1
5.4.2
5.4.3
5.4.4
I/O Interrupts ................................................................................................. 296
Outbound I/O Access ............................................................................ 276
Inbound I/O Access............................................................................... 276
FSB Overview....................................................................................... 278
FSB Dynamic Bus Inversion.................................................................... 279
FSB Interrupt Overview ......................................................................... 279
5.1.3.1
Memory Size ........................................................................................ 280
DIMM Technology and Organization......................................................... 280
DIMM Configuration Rules ...................................................................... 281
5.2.3.1
5.2.3.2
Memory RAS ........................................................................................ 282
5.2.4.1
5.2.4.2
5.2.4.3
5.2.4.4
5.2.4.5
5.2.4.6
5.2.4.7
DIMM Memory Configuration Mechanism .................................................. 285
DRAM ECC Code ................................................................................... 286
5.2.6.1
DDR2 Protocol ...................................................................................... 287
5.2.7.1
5.2.7.2
5.2.7.3
5.2.7.4
5.2.7.5
Memory Thermal Management................................................................ 287
5.2.8.1
5.2.8.2
5.2.8.3
5.2.8.4
5.2.8.5
5.2.8.6
5.2.8.7
Electrical Throttling ............................................................................... 290
XAPIC Interrupt Message Format ............................................................ 292
XAPIC Destination Modes ....................................................................... 292
5.4.2.1
5.4.2.2
5.4.2.3
Interrupt Redirection............................................................................. 294
5.4.3.1
5.4.3.2
5.4.3.3
End Of Interrupt (EOI) .......................................................................... 295
Upstream Interrupt Messages ................................................... 279
Permissible Configurations ........................................................ 281
Memory Technology................................................................. 282
Memory Sparing...................................................................... 282
Data Poisoning in Memory ........................................................ 283
Patrol Scrubbing...................................................................... 283
Demand Scrubbing .................................................................. 283
Normal Correction ................................................................... 284
Enhanced Correction................................................................ 284
Single Device Data Correction (SDDC) Support............................ 284
Inbound ECC Code Layout for Memory Interface .......................... 286
Posted CAS ............................................................................ 287
Refresh .................................................................................. 287
Access Size ............................................................................ 287
Transfer Mode......................................................................... 287
Invalid and Unsupported DDR Transactions ................................. 287
Closed Loop Thermal Activate Throttle Control ............................ 287
Open Loop Global Throttling...................................................... 288
Global Activation Throttling Software Usage ................................ 288
Dynamic Update of Thermal Throttling Registers ......................... 289
General Software Usage Assumptions ....................................... 289
Dynamic Change Operation for Open Loop Thermal Throttling (OLTT) .
289
Disabling Open Loop Throttling.................................................. 290
Physical Destination Mode (XAPIC) ............................................ 292
Logical Destination Mode (XAPIC) .............................................. 293
XAPIC Interrupt Routing ........................................................... 293
XTPR Registers ....................................................................... 294
Redirection Algorithm .............................................................. 294
XTPR Update .......................................................................... 295
Intel
®
5100 MCH Chipset—Contents
Order Number: 318378-005US
July 2009