HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 326

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

1. To assure that PCI enumeration has completed, an I/O device should not send a DMA Engine query until its own device driver
5.16
Note:
5.16.1
5.16.2
Note:
Note:
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Datasheet
326
has been loaded. Otherwise the DMA Engine device may not be able to respond.
®
5100 Memory Controller Hub Chipset
Programming Flow
This section describes the steps for a client to use DMA Engine facilities.
Locking of CB MMIO space is undesirable, unpredictable, and might result in deadlock.
Thus, an attempt to generate a locked request to CB MMIO location is invalid.
General
The I/O device driver queries the DMA Engine driver to learn the location of DMA
Engine registers. The DMA Engine device driver needs to know the address of the I/O
device so it can determine which PCI Express* port serves the device and thus select
the correct set of per-port registers. Additionally, I/O device drivers will request use of
DMA Engine resource via the DMA Engine driver.
Using DMA
In the following discussion, the term Device means I/O device and its I/O device driver.
The DMA Engine driver reads
checks how many DMA channels are supported. A value of zero indicates no DMA
support.
The client requests and the DMA Engine driver grants permission to use a particular
channel. The client accesses DMA Engine hardware through the DMA Engine driver.
The DMA Engine driver should not directly expose
Interrupt Control”
Engine device (see
If the client successfully claims ownership of a DMA channel, then the client writes the
CHANCTRL to configure the channel’s DMA operation.
Client writes the
Register”
The DMA channel is now operational.
Client reads the
maximum transfer capacity for the DMA channel.
To start DMA operation, the client builds DMA descriptors in main memory, writes
Section 3.11.23.4, “CHAINADDR[3:0] - Descriptor Chain Address Register”
the first descriptor in the chain, and then initiates the DMA transfer in
3.11.23.5, “CHANCMD[3:0] - DMA Channel Command Register”
To avoid snooping cycles, the client can set Destination address snoop control and
Source address snoop control in the Descriptor and Descriptor address snoop control in
CHANCTRL. However, the client must make sure that processors do not access those
memory locations to avoid coherency problems resulting from processor caching. Thus
the I/O driver must not access that memory. Even then, when the I/O driver first
allocates the memory, locations might may reside in a processor’s cache due to a
previous process owning the memory. Before using the no-snoop options, the client
must make sure caches are flushed. One way to flush all caches for a particular
memory buffer is to program the DMA channel to move the buffer to itself (or move the
to specify where the DMA channel writes the Completion Status.
Section 3.11.22.2, “XFERCAP - Transfer Capacity”
Section 3.11.23.6, “CHANCMP[3:0]: Channel Completion Address
register. The I/O driver registers its interrupt handler with the DMA
Section 5.16.3, “Interrupt
Section 3.11.22.1, “CHANCNT - Channel Count”
Intel
Handling”).
®
5100 MCH Chipset—Functional Description
Section 3.11.22.3, “INTRCTRL -
Order Number: 318378-005US
register to learn the
Section
to indicate
and
July 2009