HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 212

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.9.9
3.9.9.1
3.9.9.2
Intel
Datasheet
212
®
5100 Memory Controller Hub Chipset
Memory Control Debug Registers
These registers are used to inject bit errors into memory arrays for memory error
detection testing. These registers allow the user to corrupt individual memory bits.
Address matching error injection can be programmed to occur on demand writes only.
It will not occur for writes that occur as a result of scrubbing/sparing.
MEM[1:0]EINJMSK0: Memory Error Injection Mask0 Register
This register contains the error injection mask register to determine which bits get
corrupted for error detection testing.
MEM[1:0]EINJMSK1: Memory Error Injection Mask1 Register
This register contains the error injection mask register to determine which bits get
corrupted for error detection testing.
Device:
Function:
Offset:
29:28
25:10
9:5
4:0
Bit
31
30
27
26
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
16
1
208h, 200h
Default
01
0h
0h
0h
0
0
0
0
ADDRMATCHEN: Address Match Enable - determines if address match is
enabled for error injection:
0: Address match disabled (default)
1: Address match enabled
RESPDONEDIS: Response Function Done Disable Signal
This bit will disable the done signal returned from the response logic.
0: Use the “Done” return signal to remove the assertion
1: Disable the “Done” signal from alerting the response function
HLINESEL: Half cache line selection
00: Reserved
01: Selects lower half cache line for error injection on transfer 0 and 1 using First
and/or Second device pointers.
10: Selects upper cache line for error injection on transfer 2 and 3 using First and/
or Second device pointers.
11: Select both upper and lower cache lines to inject errors based on the First and
Second device pointers. The same masks are applied to both halves.
EINJEN: Error injection enable
0: Disable error injection
1: Enable error injection
EINJFUNCTSEL: Error Injection Function Select
0: Select DINJ0 response function.
1: Select DINJ1 response function.
XORMSK: XOR mask bit for first device pointer
[25:18]: XOR mask for transfer 1 (lower half cache line) or 3 (upper half cache
line).
[17:10]: XOR mask for transfer 0 (lower half cache line) or 2 (upper half cache
line).
SEC2RAM: Second device pointer location [17:0]
There are 18 - x8 device locations across both DIMM channels [1:0] that the XOR
mask can be applied.
FIR2RAM: First device pointer location [17:0]
There are 18 - x8 device locations across both DIMM channels [1:0] that the XOR
mask can be applied.
Intel
Description
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009