HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 17

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Contents—Intel
July 2009
Order Number: 318378-005US
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100 Software Model Dependencies.................................................................................. 323
101 INTRCTRL Interpretation ......................................................................................... 328
102 Incoming PCI Express* Requests ............................................................................. 331
103 Incoming PCI Express* Completions ......................................................................... 332
104 Outgoing PCI Express* Requests .............................................................................. 332
105 Outgoing PCI Express* Completions ......................................................................... 332
106 PCI Express* Transaction ID Handling....................................................................... 333
107 PCI Express* Attribute Handling............................................................................... 334
108 MCH Ordering Implementation ................................................................................. 340
109 Intel
110 Reset Sequences and Durations ............................................................................... 346
111 SMBus Transaction Field Summary ........................................................................... 349
112 SMBus Address for Intel
113 SMBus Command Encoding ..................................................................................... 355
114 Status Field Encoding for SMBus Reads ..................................................................... 356
115 Intel
116 I/O Port Registers in I/O Extender Supported by
117 PCI Hot Plug* Signals on Virtual Pin Port ................................................................... 364
118 Decode Table in Intel
Timing Characteristics of RANKTHRESHOLD ............................................................... 209
RANKTHRESHOLD Recommended Settings ................................................................ 210
Device 8, Function 0, DMA Engine Configuration Map .................................................. 216
Device 8, Function 1, DMA Engine DMABAR MMIO Registers (General, DMA Channel 0) Mapped
through Configuration............................................................................................. 217
Device 8, Function 1: DMABAR MMIO Channel 2 and 3 Registers .................................. 218
Device 8, Function 1: DMABAR MMIO Channel 3 Registers ........................................... 219
Device 8, Function 1: Per Port-specific Registers for Ports 2 and 3 ................................ 220
IV Vector Table for DMA Errors and Interrupts ........................................................... 230
DMA Memory Mapped Register Set Locations ............................................................. 240
Memory Segments and Their Attributes..................................................................... 261
PAM Settings ......................................................................................................... 263
Low Memory Mapped I/O ........................................................................................ 266
I/O APIC Address Mapping ...................................................................................... 267
Intel
Address Disposition for Processor ............................................................................. 271
Enabled SMM Ranges.............................................................................................. 272
SMM Memory Region Access Control from Processor ................................................... 273
Decoding Processor Requests to SMM and VGA Spaces................................................ 273
Address Disposition for Inbound Transactions ............................................................ 274
DBI[3:0]#/Data Bit Correspondence......................................................................... 279
SDRAM Signal Allocations for Different Technologies ................................................... 282
Memory Poisoning Table ......................................................................................... 283
SPD Addressing ..................................................................................................... 286
Electrical Throttle Window as Function of DIMM Technology ......................................... 290
XAPIC Data Encoding.............................................................................................. 292
Intel
XAPIC Interrupt Message Routing and Delivery .......................................................... 293
Chipset Generated Interrupts................................................................................... 301
PCI Express* Link Width Strapping Options for Port CPCI Configuration in Intel
Controller Hub Chipset............................................................................................ 312
Options and Limitations .......................................................................................... 312
Intel
PCI Express* Credit Mapping for Inbound Transactions ............................................... 319
PCI Express* Credit Mapping for Outbound Transactions ............................................. 319
Intel
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5100 Memory Controller Hub Chipset Memory Mapping Registers ........................ 270
5100 Memory Controller Hub Chipset
5100 Memory Controller Hub Chipset Lane Reversal Matrix ................................ 316
5100 Memory Controller Hub Chipset Reset Classes .......................................... 343
5100 Memory Controller Hub Chipset Supported SPD Protocols ........................... 360
5100 Memory Controller Hub Chipset .............................................................. 363
5100 MCH Chipset
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5100 Memory Controller Hub Chipset for TPM Locality ................ 365
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5100 Memory Controller Hub Chipset-based Platform ............. 355
Intel
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5100 Memory Controller Hub Chipset
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5100 Memory
Datasheet
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