HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 33

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
2.0
July 2009
Order Number: 318378-005US
Signal Description
This section provides a detailed description of MCH signals. The signals are arranged in
functional groups according to their associated interface.
Memory Controller Hub Chipset Signal Diagram 32 GB Mode”
5100 Memory Controller Hub Chipset Signal Diagram 48 GB Mode”
in a block diagram format for 32 GB and 48 GB modes. Throughout this section the
following conventions are used:
The terms assertion and deassertion are to avoid confusion when working with a mix of
active-high and active-low signals. The terms assert, or assertion, indicates that the
signal is active, independent of whether the active level is represented by a high or low
voltage. The terms deassert, or deassertion, indicates that the signal is inactive.
Signal names may or may not have a “#” appended to them. The “#” symbol at the
end of a signal name indicates that the active, or asserted state occurs when the signal
is at a low voltage level. When “#” is not present after the signal name, the signal is
asserted when at the high voltage level.
Differential signal pairs adopt a “{P/N}” suffix to indicate the “positive” (P) or
“negative” (N) signal in the pair. If a “#” is appended, it is appended to the positive and
negative signals in a pair.
Typical frequencies of operation for the fastest operating modes are indicated. No
frequency is specified for asynchronous or analog signals.
Some signals or groups of signals have multiple versions. These signal groups may
represent distinct but similar ports or interfaces, or may represent identical copies of
the signal used to reduce loading effects.
Curly-bracketed non-trailing numerical indices, e.g., “{X/Y}”, represent replications of
major buses. Square-bracketed numerical indices, e.g., “[n:m]”, represent functionally
similar but logically distinct bus signals; each signal provides an independent control,
and may or may not be asserted at the same time as the other signals in the grouping.
In contrast, trailing curly-bracketed numerical indices, e.g., “{x/y}”, typically represent
identical duplicates of a signal; such duplicates are provided for electrical reasons.
The following notations are used to describe the signal type:
I
O
I/O
s/t/s
The signal description also includes the type of buffer used for the particular signal:
AGTL+
LVTTL
®
5100 MCH Chipset
Input pin
Output pin
Bi-directional Input/Output pin
Sustained Tristate. This pin is driven to its inactive state prior to
tristating.
Open Drain AGTL+ interface signal. The MCH integrates AGTL+
termination resistors, and supports VTT from 1.05 V to 1.2 V.
Low Voltage TTL 3.3 V compatible signals
Intel
®
Figure 2, “Intel® 5100
5100 Memory Controller Hub Chipset
and
Figure 3, “Intel®
illustrate the signals
Datasheet
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