HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 279

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.1.2
Table 87.
5.1.3
5.1.3.1
July 2009
Order Number: 318378-005US
FSB Dynamic Bus Inversion
The Intel
when receiving data from the processor. DBI limits the number of data signals that are
driven to a low voltage on each quad pumped data phase. This decreases the worst-
case power consumption of the MCH. The DBI[3:0]# signals indicate if the
corresponding 16 bits of data are inverted on the bus for each quad pumped data
phase.
DBI[3:0]#/Data Bit Correspondence
When the processor or the Intel
is analyzed. If more than eight of the 16 signals would normally be driven low on the
bus, the corresponding DBI# signal will be asserted and the data will be inverted prior
to being driven on the bus. When the processor or the MCH receives data, it monitors
DBI[3:0]# to determine if the corresponding data segment should be inverted.
FSB Interrupt Overview
The Intel
bus interrupt delivery mechanism is not supported. Interrupt-related messages are
encoded on the FSB as “Interrupt Message Transactions.” In the Intel
Chipset, FSB interrupts may originate from the processor on the system bus, or from a
downstream device on the Enterprise South Bridge Interface (ESI). In the later case,
the MCH drives the Interrupt Message Transaction onto the system bus.
In the Intel
generated as upstream ESI memory writes. Furthermore, PCI Local Bus Specification,
Rev. 2.3 defines Message Signaled Interrupts (MSI) that are also in the form of
memory writes. A PCI 2.3 device may generate an interrupt as an MSI cycle on its PCI
bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be directed to
the IOxAPIC which in turn generates an interrupt as an upstream ESI memory write.
Alternatively, the MSI may be directed directly to the FSB. The target of an MSI is
dependent on the address of the interrupt memory write. The MCH forwards inbound
ESI and PCI (PCI semantic only) memory writes to address 0FEEx_xxxxh to the FSB as
Interrupt Message Transactions.
Upstream Interrupt Messages
The MCH accepts message-based interrupts from PCI (PCI semantics only) or ESI and
forwards them to the FSB as Interrupt Message Transactions. The interrupt messages
presented to the MCH are in the form of memory writes to address 0FEEx xxxxh. At the
ESI or PCI interface, the memory write interrupt message is treated like any other
memory write; it is either posted into the inbound data buffer (if space is available) or
retried (if data buffer space is not immediately available). Once posted, the memory
write from PCI or ESI to address 0FEEx xxxxh is decoded as a cycle that needs to be
propagated by the MCH to the FSB as an Interrupt Message Transaction. The write
nature of the message “pushes” all applicable pre-interrupt traffic through to the Intel
5100 MCH Chipset core, and the Intel
that the subsequent APIC message cannot pass any posted data already within the
Intel
®
DBI[3:0]#
5100 MCH Chipset.
DBI0#
DBI1#
DBI2#
DBI3#
®
®
®
5100 MCH Chipset supports Dynamic Bus Inversion (DBI) when driving and
5100 MCH Chipset supports FSB interrupt delivery. The legacy APIC serial
®
5100 MCH Chipset
5100 MCH Chipset the ICH9R contains IOxAPICs, and its interrupts are
D[31:16]#
D[47:32]#
D[63:48]#
Data Bits
D[15:0]#
®
5100 MCH Chipset drives data, each 16-bit segment
®
5100 MCH Chipset core architecture guarantees
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH
Datasheet
279
®